RE: Email Ballot due Monday June 18th

Hi Dmitry,

You write regarding http://www.eda-twiki.org/svdb/view.php?id=4146

   "Should also be mentioned new definition of assertion sampling and enhancements in assertions and checkers"

As you can verify in my http://bradpierce.wordpress.com/2011/11/22/sv12-whats-in-store-for-systemverilog-2012 , I agree that important things were done for assertions in SV12.

But could you help me with the specific language you want in the abstract? To me, a 'new definition' suggests backward incompatibility, but I think you were talking about 'assert final'.

And 'enhancements in assertions and checkers' seems too generic to me. Instead, could you list a specific enhancement that would encourage the community to promptly move to SV12? Are you talking about making checkers more like modules?

Thanks,

-- Brad

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