Mantis 4143: Wrong interface example in clocking blocks

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mantis --> view.php?id=4143 :

Surya:

In section 14.9 (Interfaces and clocking blocks) of SV 2009 LRM, there
is a following example:

[...]
program test( bus_A.test a, bus_B.test b );
clocking cd1 @(posedge a.clk);
input data = a.data;
output write = a.write;
inout state = top.cpu.state;
endclocking
clocking cd2 @(posedge b.clk);
input #2 output #4ps cmd = b.cmd;
input en = b.enable;
endclocking
[...]

It seems the the text mentioned in red is illegal, because 'clk' and
'cmd' are explicitly listed in modport 'test'. Here is the corresponding
LRM snippet (page no 691 of SV 2009 LRM):
A modport may be used to restrict access to objects declared in an
interface that are referenced through a port connection or virtual
interface by explicitly listing the accessible objects in the modport.
However, objects that are not permissible to be listed in a modport
shall remain accessible.

Fix should be done in either position.

Shalom:

The 'red' in Surya's mail refers to a.clk, b.clk, and b.cmd.(The red got
turned to black.)

I think the fix should be to add clk and cmd to the modports.

Question: can this be fixed in this revision of the LRM?

Thanks,

Shalom

Shalom Bresticker
Intel LAD DA, Jerusalem, Israel
+972 2 589 6582 (office)
+972 54 721 1033 (cell)
    linkedin --> shalombresticker

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