Inputs to Binding outlines

Hi all,

In our last meeting Cadence proposed to send out sub-topics that is
would serve as 
inputs to authors of Binding outlines.

Please find below the list of sub-topics that come to our mind. We
believe the outlines would shelve
details on these aspects.

 1) Forms of binding foreign models to Verilog
           a)  MIP instantiation 
           b)  bind directive

 2) Syntax of binding foreign models to Verilog

 3)  Verilog contexts where foreign models could be bound into.

 4)  Foreign name/design unit references and mapping/conflicts

 5)  Library search rules 

 6)  Implications on hierarchical references.

 7)  Data type compatibility of ports and parameters

 8)  Object compatibility of ports and parameters

 9)  Mode compatibility of port and parameters

10) Kinds of expressions in port and parameter connections

11) Implication of configuration rules

12) Port and parameter association mechanisms and rules

13) Compilation order and dependency 

14) Elaboration model


thanks and regards,
nss


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