FW: more Binding questions

 

________________________________

From: N.S. Subramanian [mailto:subns@cadence.com] 
Sent: Wednesday, April 18, 2007 6:01 AM
To: Logie.Ramachandran@synopsys.COM
Cc: Amit Kohli
Subject: more Binding questions


 
Logie,
 
Please find attached some more questions related to binding mostly from
SV-VHDL perspective.
 
I apologize for the delay.
 
thanks,
nss
 
 
 
Here are Questions that need to be addressed by the mixed language
binding solution:
 
Name space related Questions:
 
1)  Is there a need to define a separate name space when binding to
foreign language components. If not,
     should we enhance the port name space to allow connections between
names in a foreign 
     language name space and a SV name space.
 
2)  How do we refer to foreign language objects in SV name spaces ? Note
that VHDL names are case
     insensitive while Verilog names are case sensitive.
 
3)  How do we represent SV and VHDL design units in the common library ?
Do we need to perform some
     automatic conversions when reading from or writing to the library ?
How do we resolve conflicts in the
     library. 
 
Configuration related  Questions:
 
1)  Do we need to enhance the Verilog configurations (ie. config)  for
VHDL design entities. If so, 
 
    a)  How do we enhance the Verilog configuration mechanism to
configure Verilog instances
         that are bound to VHDL design entities.
 
    b)  How do we enhance Verilog configuration to configure VHDL design
instances that are
         bound to VHDL or Verilog design units, but under a Verilog
hierarchy.
  
    c)  Should we allow Verilog configs to configure pure VHDL design
units  ?
 
2)  Do we need to enhance the Verilog library search order to allow VHDL
libraries ?
 
3)  Do we permit VHDL architectures and configurations to be referenced
in the Verilog use clauses ? 
 
4) Do we need to extend SV hierarchical configurations to VHDL design
units and instances ?

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