[Fwd: Re: Binding Followup]

From: John Shields <John_Shields_at_.....>
Date: Wed Apr 18 2007 - 08:30:21 PDT

Hi,

This was meant to be posted to the reflector as well. Sorry.

Regards, John

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Hi Geoffrey,

The question was refering to VHDL-AMS connections.  There is no mechanism equivalent to connect rules and connect blocks in VHDL-AMS.  Interestingly, there was a committee mtg for VHDL-AMS yesterday at DATE.  There is a language design effort commencing to extend vhdl-ams to support these kinds of connections. I co-authored a white paper on this extension for FDL  a couple of years ago.  It is a legitimate question.  I agree there is no question about V-AMS and SV.

Regards, John

Geoffrey.Coram wrote:

Hi, Logie -
I'm somewhat puzzled/troubled by the implication in your
message that there is a "SystemVerilog-AMS boundary".

In particular, since Verilog-AMS has modules and parameters
defined by the same rules as Verilog, what boundary is there?
There aren't any special rules necessary for instantiating
AMS modules, and the parameter binding rules of AMS are
those of Verilog.

AMS parameters are Verilog parameters (AMS added strings
to 1364, but did so in the same way 1800 did).

AMS variables are the same as Verilog's.

AMS port connections already support the same named or
positional connections as SV, and AMS could naturally be 
extended to allow implicit .name and *.port connections.

  

6)   Is it OK to connect a VHDL-AMS terminal to a SV digital net?
     Inside VHDL-AMS, a terminal can be connected only to a terminal.
     However, in VERILOG-AMS, language does allow an analog node to be
     connected to a digital net and the language provides a mechanism to
     automatically insert a connect module (D2A or A2D converter) at
     Analog/Digital boundary. Which rule to follow : VERILOG-AMS or
VHDL-AMS?
    

I don't understand why there is a question; existing AMS
tools allow connections from an analog node to a 1364-Verilog
digital net, so for backwards compatibility, aren't you
required to follow the Verilog-AMS rule?

I can think of a couple extensions in AMS that need to be handled:
1) wreal nets
2) parameter aliases (built-in Spice models accept parameters by
more than one name, eg "vt0" (vee-tee-zero) and "vto" (vee-tee-oh))
3) paramsets, which are sort of like Spice .model cards on steroids;
several paramsets can have the same name and the simulator is
responsible for picking the one that fits the instance
(lmin < L_instance < lmax).

(Kevin can probably help me out with any others I missed.)

-Geoffrey

  

Received on Wed Apr 18 08:30:41 2007