Binding Followup

Hi team

I have collated all the questions received so far into 4 buckets.

Thanks

Logie. 

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Object types for binding
------------------------

1)   With respect to each language, what are the design units of that
     language and which may be instantiated in which other language?

     For example, A VHDL primary design unit may be a package header, an
     entity, or a configuration.  Package bodies and architectures are
     secondary design units in VHDL.  A VHDL instance is either a
package
     instance( header plus body, if any) or a component instantiation (
     entity/architecture pair).

2)   What is the basic boundary between languages, i.e., are design
units
     expected to be written entirely in the same language or can foreign
     language constructs be used directly within a design unit?

3)   Are there any restrictions  on the final structure of a mixed
     language elaborated design? May any instance be a design unit from
any
     other language?

4)    What other kinds of objects would you like to connect in an
      instantiation that crosses  (functions/tasks etc)
      a) SystemVerilog-VHDL boundary
      b) SystemVerilog-SystemC boundary
      c) SystemVerilog-AMS boundary

Datatype mapping 
----------------
1)   Each language supports parameterization of design units and
     mechanisms to bind those parameters to static values at
elaboration.

     a) What are the forms of declaring the parameterization of a design

        unit in each language?  
     b) What are the mechanisms by which such parameters 
        may be bound in each language?  
     c) What binding mechanisms with what restrictions
        can be applied to an instance bound to a foreign design unit?
 
2)   What kinds of data types would you like to see supported on 
              i. parameters
             ii. nets/signals
            iii. variables
      across 
      a) SystemVerilog-VHDL boundary
      b) SystemVerilog-SystemC boundary
      c) SystemVerilog-AMS boundary
      
4)   List the data type mappings for  
              i. parameters
             ii. nets/signals
            iii. variables
     across
      a) SystemVerilog-VHDL boundary
      b) SystemVerilog-SystemC boundary
      c) SystemVerilog-AMS boundary

 

5)    What are the compatibility rules for VHDL-AMS and the
      corresponding Verilog-AMS discipline for the natures 
      declared in the IEEE.electrical_systems package

Binding Syntax
--------------
1)    In a multilanguage environment do we need to define  special
attributes 
      in the instantiation  that
      indicates if a module is coming from 
      (a) different language, 
      (b) which one? 


2)   How will we extend "extern" modules for
      a) SystemVerilog-VHDL boundary
      b) SystemVerilog-SystemC boundary
      c) SystemVerilog-AMS boundary


3)   SystemVerilog allows instantiation using 
         i. positional port connections
        ii. named port connections
       iii. implicit .name port connections
        iv. implicit *.port connections
      How will we extend the above connection types for
		a) instantiation of VHDL components
      	b) instantiation of SystemC components
      	c) instantiation of AMS components


4)   What kind of expressions will we allow (if any) on the port 
     connections. (eg. partselects, concats). 

5)   With respect to each language, what are the forms of instantiation
of
     a design unit in that language and which forms are suitable for
     instantiation of foreign design unit?

     For example, in VHDL, a package use clause implies package
instantiation
     and components may be instantiated by direct e/a instantiation, a
     component instantiation, or a configuration instantiation.  A
component
     instantiation may be configured by a component specification, a
default
     binding rule, or an external configuration.

6)   Is it OK to connect a VHDL-AMS terminal to a SV digital net?
     Inside VHDL-AMS, a terminal can be connected only to a terminal.
     However, in VERILOG-AMS, language does allow an analog node to be
     connected to a digital net and the language provides a mechanism to
     automatically insert a connect module (D2A or A2D converter) at
     Analog/Digital boundary. Which rule to follow : VERILOG-AMS or
VHDL-AMS?


Compilation/Elaboration Requirements
-------------------------------------

1)   In all languages, design units are compiled into libraries and
     subsequently, a design may be elaborated from these design units.
Are
     there any restrictions on the composition of a library with respect
to
     the kinds/language of design units it may contain?

2)   What order of compilation rules apply in a mixed language context?

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