RE: Survey Questionnaire: Draft version

Logie, John,

3.16 does not really require any extensions to the VHDL language. But it
does require clarifications
in the SystemVerilog language syntax and semantics pertaining to how
foreign objects and expressions thereof
will be specified and interpreted.

My purpose of 3.17 is two fold 

a)  Like John mentioned, I would like SV instances to have access to
interface objects irrespective of where
    they occur in the mixed language hierarchy. If it is already
captured in a more general form, I am ok. 

b)  I see some early discussion in the VHDL standards committee
regarding interfaces and I am hoping 
    this survey might influence the direction taken by VHDL as well as
interoperability between
    interfaces of the two languages. 

The intention of this question is to really ask the user if he sees
value in having interfaces as 
first class VHDL objects and if so why. 

thanks and regards,
nss
   

-----Original Message-----
From: John Shields [mailto:John_Shields@mentor.com] 
Sent: Tuesday, February 13, 2007 12:09 AM
To: Logie Ramachandran
Cc: N.S. Subramanian; sv-xc@eda.org
Subject: Re: Survey Questionnaire: Draft version

Hi,

3.16 is a good question and does not necessarily imply changes to VHDL.

3.17 on the other hand, has 2 issues.  First, interfaces do not have a
meaningful object kind in VHDL, so it absolutely requires extensions.  
Second, I don't understand the purpose of the question.  Is the goal to
pass an interface through a VHDL instance down to another SV instance
without affecting or being affected by the VHDL instance?  (If so, I
asked a more general version of that question in my feedback).

Or is it to make interfaces (with some restrictions) automagically 
connect to some VHDL structural port(s), sort of an automatic adaptor?

Or is it even to make interfaces a first class object in VHDL so the
connection has very rich semantics? Anyway, without clearing that up, I
don't think it is the right question.  If it is to have semantics within
the VHDL block, then any request for it should explain why they want it,
what use case is envisioned.

Regards, John

Logie Ramachandran wrote:
> Hi NSS,
>
> I was wondering whether 3.16 and 3.17 are within the scope of this 
> committee. Dont these scenarios need extensions to VHDL.
>
> Thanks
>
> Logie.  
>
> -----Original Message-----
> From: N.S. Subramanian [mailto:subns@cadence.com]
> Sent: Wednesday, February 07, 2007 9:25 PM
> To: Logie Ramachandran
> Cc: N.S. Subramanian
> Subject: RE: Survey Questionnaire: Draft version
>
> Logie,
>
> I had some additional survey questions for the VHDL section:
>
> 3.16 Would you like to extend SystemVerilog bind to create SV 
> module/interface instances in
>      VHDL blocks and instances?
>
> 3.17 Would you like to be able to pass SystemVerilog interfaces to 
> VHDL through port connections ?
>
> thanks and regards,
> nss
>
>
>
> -----Original Message-----
> From: owner-sv-xc@eda.org [mailto:owner-sv-xc@eda.org] On Behalf 
> Ofoesn't quite Logie Ramachandran
> Sent: Monday, February 05, 2007 11:12 PM
> To: arnab_saha@mentor.com; John Shields; Kathy McKinley; Amit Kohli; 
> Roy, Somdipta Basu; Ulrich Holtmann
> Cc: sv-xc@eda.org
> Subject: Survey Questionnaire: Draft version
>
> Hi Team,
>
> This took much longer than I expected. I have put together the 
> combined questionnaire making sure that we get a consistent look and 
> feel across the sections.
> I have merged the DPI questions into the SystemC and VHDL section.  
>
> I have also tried to keep this as a txt file so that it can be parsed 
> by a script easily.
>
> Please review the sections and make sure that I have captured all the 
> feedback so far. Suggest any changes in format/questions over email.
>
> Thanks
>
> Logie. 
>
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>   

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