Hi,
I've reviewed the questionnaire. Overall, I like it. Even if users
don't give us great feedback, we've considered questions we want to
answer. Logie asked me
to look at use model and overall questions and suggest improvements.
I had a specific goal to to avoid encouraging "kitchen sink" answers
whereby participants ask for everything because they are not sure what
they need or they are afraid we will take a narrow minded approach to
the analysis. It could still happen, but this is my feedback. I
propose some changes in the introduction, modifications and addition to
the general section questions, additions to the SV-VHDL section, and a
final section that has open-ended questions.
In the Purpose and General Section, my changes are in
italics.
Regards,
John Shields,
Mentor Graphics
Survey
Questionnaire: SystemVerilog interfaces to other HDL
languages
Purpose:
The purpose of this questionnaire is to understand the importance of
various topics that deal with SystemVerilog
interoperability as
it pertains to other HDL languages. We focus on three HDL languages in
this survey (SystemC, VHDL and AMS).
Your inputs will help the SV-XC committee focus on the important items
that will have direct impact on your design
methodology.
We
will do a comprehensive technical analysis, but your requirements and
their priority to you will help us. It will allow us make better
tradeoffs on usability and phase the development of the specification
effectively. Be cautious in asking for detailed aspects because you
are not sure if you might need them. Explaining why a choice was made
can be as important as the choice itself. You are encouraged to
elaborate on your answer to any question or add additional feedback not
specifically requested.
For each of the questions please replace the [] at the
beginning
of the
line with your importance rating. Use the following codes to make it
consistent.
[1] Extremely Important
[2] Important
[3] Not that important
[4] Not required
There are four sections in this questionnaire. Section 1 addresses
"General" questions on interoperability of SystemVerilog. Section
2 focuses on SystemC while Section 3 focusses on VHDL interaction with
SystemVerilog. Section 4 addresses AMS issues as it pertains to
SystemVerilog.
Thanks in advance for your help. If you would like to participate in
the SV-XC committee please send email to
logie@synopsys.com
or
somdipta@ti.com.
================================================================
Section 1: General
================================================================
1.1 Do you see interoperability of languages as an issue that
needs to be addressed. If so what kinds of interoperability
issues?
[] 1.1.1 SystemC <-> SystemVerilog interoperability
[] 1.1.2 VHDL <-> SystemVerilog interoperability
[] 1.1.3 AMS <-> SystemVerilog interoperability
[] 1.1.4 The digital subset inter-operating seamlessly( SV, VHDL,
SystemC )
[] 1.1.5 All four inter-operating seamlessly (AMS, VHDL, SV, SystemC)
--------------------
1.2 Which of the following needs standardization?
[] 1.1.1 SystemC <-> SystemVerilog interoperability
[] 1.1.2 VHDL <-> SystemVerilog interoperability
[] 1.1.3 AMS <-> SystemVerilog interoperability
[] 1.1.4 The digital subset inter-operating seamlessly( SV, VHDL,
SystemC )
[] 1.1.5 All four inter-operating seamlessly (AMS, VHDL, SV, SystemC)
1.3 Some aspects of interoperability may be specified by
providing a definition of
expected behavior while others may require one or more of the
base languages to
add new features, change simulation semantics, or even change
in a manner that
is not backward compatible. As guidelines, please rank the
following approaches:
[ ] 1.3.1 strictly preserve the current definition and semantics of
all languages
[ ] 1.3.2 only make changes to SV language as needed
[ ] 1.3.3 propose interoperability features contingent upon changes to
non SV languages
[ ] 1.3.4 where changes are desirable, always preserve backward
compatibility
[ ] 1.3.5 guarantee that a model behaves the same in a mixed language
environment as
they do in a single language environment
================================================================
Section 3:VHDL
================================================================
3.16 Both VHDL and SV support strong typing and type safety for
user-defined data types
such as enumerations, structures,records, unions, and classes. This
guarantees that erroneous
operations and illegal values for the type do not occur in objects
unless specifically intended,
e.g., by casting. How important is it to provide mechanisms to preserve
type safety:
[ ] 3.16.1 For enumerations and structure/record types
[ ] 3.16.2 For all user-defined types, where both languages require it
[ ] 3.16.3 For all data types that do not have a one-to-one compatible
type between the languages
3.17 There are various mechanisms that could support type safety, where
required. Please indicate
which you would like to see:
[ ] 3.17.1 Sharing of types declared from an inter-operable package
written in SV
[ ] 3.17.2 Sharing of types declared from an inter-operable package
written in VHDL
[ ] 3.17.3 Sharing of types declared via a hierarchical reference
[ ] 3.17.4 Explicitly declaring(somehow) that 2 distinct types are
equivalent, subject to
appropriate rules
[ ] 3.18 There are some kinds of objects that could have no equivalent
in the other language,e.g, a
multidimensional array in VHDL or a SV class. Is there a need for a
mechanism to transparently
pass an object of such a kind as a parameter or a port? For example,
is there a need to pass a
class from SV through a VHDL to another SV child instance?
================================================================
Final Section
================================================================
The previous questions are feature oriented and, given a good
understanding of the details,
should insure we don't leave out an important feature. They may not
express all your requirements
and they do not allow you to explain what use models you envision for
developing design and
verification models that lead to your need for mixed language
interoperability. The following
questions suggest ways to complete your feedback. Provide answers if
appropriate to express
your needs.
What levels of abstraction and role do your existing models have for
each HDL language that
you use? How do they need to work together today? How do you
anticipate this use model
changing over time?
-----
-----
At a high level, what do you expect to be able to do with more mixed
language interoperability
that you are currently able to do today? How will it change your
design methodology
over time?
-----
-----
While one can idealize how completely and seamlessly they would like
everything to inter-operate,
not everything is practical. At some level, the alternative is
enhancing one particular language
to meet a need, or changing to a different language. Are there some
aspects of interoperability
that you believe are not appropriate to do? Why?
-----
-----
Is there anything else on this topic that you would like to say?
-----
-----
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Received on Tue Feb 6 11:21:32 2007