Unapproved minutes of the SV-XC Committee Meeting Date: Wednesday, Jan 24, 2007 Time: 08:00am - 10:00 am PST Attendees ------------------------------------------------ 0011 1122 2120 4006 0000 7766 ------------------------------------------------ pp-p Somdipta Roy (TI) pppp Logie Ramachandran (Synopsys) pppp Ulli Holtmann (Synopsys) pppp Tapan Halder (Synopsys) pppp Bob Shur (Cadence) p--p Rob Slater (Freescale) pppp Arnab Saha (Mentor) -p-p John Shields (Mentor) pppp Amit Kohli (Cadence) pppp Kathy McKinley(Cadence) --pp Scott Cranston(Cadence) -p-p Kevin Camaron(Sonics) ---p Michael Williams (Cadence) ---p Sudip Chakrabarti (Synopsys) --p- John Stickley (Mentor) ppp- NS Subramanian (Cadence) -p-- Geoffrey Coram (Analog Devices) p--- Nitin Khurana (Cadence) p--- Micheal Rohleder (Freescale) Agenda + Review IEEE patent policy http://standards.ieee.org/board/pat/pat-slideset.ppt Kathy moves it has been read. No opposes, No abstains. Motion passes + Review minutes of the Jan 10, 2007 meeting Kathy moves we approve the minutes. Tapan seconds. No opposes. No abstains. Motion passes + Survey questionnaire feedback SystemC ------- - Rob Slater requested to add questions for simulation that consumes no time. (combinational simulation). Same delta. - Micheal/Rob to send additional question to address zero time simulation to Arnob - Events across the language (When will a SystemC event be visible to SystemVerilog and VHDL) - Consistent event handling across simulators and DPI calls. Michael/Rob to send DPI question to Amit. - Rob wanted add a question which is oppposite of 2(b). testbench in VHDL/SystemVerilog and RTL in SystemC. Arnab will add this questionniare General ------- - Kathy's feedback. For each question we should request a number that indicates priority. - Get the questionnaire consistent number. 1-High 2-Med, 3-Low, X-not important - All the owners will reframe the questions and send it out on Friday. - Tapan will send feedback on VHDL questionnaire - Final feedback to individual owners by Friday - Logie to send out consolidated questionnaire by this weekend. - Allow one more week for feedback + Dissemination of Information - Committee members discussed the dissemination of information. One idea is to decouple this work from the schedule of the System Verilog LRM. - It may not be possible to complete the work by end of the year. The minimum amount of work needed to allow instantiation of modules across languages will take up a lot of time. - Tapan indicates that we should focus on SV and Verilog AMS. + Adjournment motion Kathy moves that we adjourn, Bob seconds. + Pending Action Items - Logie to setup website and email for committee - Somdipta and Rob Slater to collect prioritization of issues from their respective companies. Jan10,2007 + Logie and Somdipta to clear up pending approvals for sv-xc mailing list + Logie to discuss with Karen/Neil on the scope of committee -------------------------------- Loganath Ramachandran Director, R&D Verification Group, Synopsys Mountain View, CA 94043 Ph: 650-584-4891 Em: logie@synopsys.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Feb 6 07:41:24 2007
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