SystemC SystemVerilog interoperability

    I had submitted a response to a survey / questionnaire regarding 
different requirements for the SC - SV interoperability. I seem to have 
misplaced the response from the group asking for further input.
     At Sonics, I am sure there are many others too, we will be having a 
need for our SV testbench to work with SC TLMs (could be timed or 
untimed) and RTL HDL. Our testbench requirement is that we will use the 
same testbench to test either model with out having to make significant 
modifications to either the testbench or the model being verified.
    We want to generate a transaction that can be passed through an 
interface (some type of channel). This channel type could be used to 
communicate with SC TLMs, a reference model in either SC or C/C++ or a 
SV transactor (BFM). It might be facilitated via some common data types 
that both languages would natively understand with out the need user 
developed adaptors or "support" code.
    With the ever, increasing use of mixed language models in simulation 
and testbench environments, many users will be faced with the burden of 
writing their own "transformation" code and connecting it through some 
type of language interface. Both of which are opportunities for 
performance loss and errors which greatly reduce re-usability and 
productivity.

Regards,

Don

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Don Ticarich			Sonics Inc.
Sr. Verification Engineer	1098 Alta Ave.
Email: dont@sonicsinc.com	Suite 101
Phone: 650.605.6127		Mountain View, CA 94043


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