FW: BOUNCE sv-xc@eda.org: Non-member submission from [Ulrich Holtmann <Ulrich.Holtmann@synopsys.com>]

Feedback from Ulli

Thanks

Logie. 

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Hi Arnab,

I propose to extend your SV/SC questionaere for these
two areas: use model and problems-encountered-so-far.

The extended questionaere is below.

Best Regards,

Ulli Holtmann



(1) At what level should a SystemC model communicate with a
  SystemVerilog model ? (choose one or more, use numbers to prioritize,
  1 = most important, 2 = less important than 1, X = not required)

  (a) Algorithmic or behavioral, not timed
  (b) Algorithmic or behavioral, timed
  (c) Communicating processes
  (d) Cycle-accurate
  (e) RTL
  (f) Other, please specify


(2) What are the most important use models for designs containing both
  SystemVerilog and SystemC ? (choose one or more, use numbers to
  prioritize, 1 = most important, 2 = less important than 1, X =
  irrelevant)

  (a) SystemC models are abstract functional models written at the
  transaction-level, e.g. bus models, CPUs, peripherals, etc.
  They are plugged into a SystemVerilog testbench and serve
  as golden reference models.

  (b) The testench is written in SystemC and is used to drive
  the DUT written in Verilog or VHDL.

  (c) SystemC models are behavioral synthesis models. They are
  used together with RTL models written in Verilog. The testbench
  is SystemVerilog.

  (d) SystemC models are written at the RTL level. They are used
  together with other RTL models that are written in Verilog,
  SystemVerilog or VHDL.

  (e) The SystemC model is a wrapper around some model written in C.
  It has an RTL interface meaning it is driven by value changes
  going through ports and is timing or cycle accurate.

  (f) The SystemC model is a wrapper around some model written in C.
  It has a TL interface meaning it is driven by function calls.
  The SystemC model has a notion of timing and may even be cycle
  accurate.

(3) Use numbers to prioritize the following based on their value
  in interfacing SystemC and SystemVerilog: (choose one or more,
  use numbers to prioritize,
  1 = most important, 2 = less important than 1, X = not required)
  (a) Pin-level(rtl) connection between SystemC and SystemVerilog
      using simple built-in types provided by each language.
  (b) Connection between SystemC and SystemVerilog using complex
      types like arrays and structs of built-in types.
  (c) Connecting objects that operate at higher level of abstraction
      as provided by each language like events, mailboxes, semaphore
      and fifos.
  (d) Hierarchically referencing external objects defined in one
      language from another.
  (e) Pass parameters across the language boundary. What type of
      parameters are these?
  (f) Other, please specify


(4) What kind of problems did you encounter so far when connecting
  SystemC with SystemVerilog? (use numbers,
  1 = frequent and difficult to resolve, 2 = infrequent and
      diffcult to resolve, 3 = frequent but easy to resolve,
  4 = no problem, 5 = not encountered so far

  (a) converting datatypes int, sc_[big]int, [big]sc_uint,
      sc_lv, sc_bv to/from SystemVerilog

  (b) converting complex datatypes such as user-defined
      structures or arrays

  (c) scheduling semantics were not as expected, e.g. value
      changes came too late or processes were executed too late

  (d) Calling blocking (=consumes simulation time) SystemC
      methods from Verilog did not work as expected or
      was difficult to do

  (e) Calling blocking (=consumes simulation time) SystemVerilog
      tasks from SystemC did not work as expected or
      was difficult to do

  (f) Differences in timescale (time resolution / time units)


(5) Additional comments ?


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