I counted 31 Master issues - so the actual number of open issues is 890. BTW, Mantis has a "tagging" feature that can eliminate the need for all these master issues. I agree with Brad and Shalom's assessment of the current situation. I do have a slightly different opinion on the process to resolve the situation. From the user's perspective (re: users not involved with the committee), I think there is frustration that SV is still a moving target. In the 1800-2005 LRM, there are still features that no tool has implemented; and in the 1800-2009 LRM, there are many more features that have yet to be implemented in any tool. Not to mention even the greater number of features that only some tools have implemented. Yes, there are way too many outstanding issues, and I don't think anyone wants to spend the rest of their lifetime resolving them. I also think most people only want to work on issues they have an interest in, either personal or company motivated. This is essentially a volunteer organization. People may work on other issues if it helps the cause of their key issues. Historically, there has not been enough participation with this standard to support two parallel efforts. My suggestion is that we open a very short timeframe to work on an amendment PAR to work on errata/clarifications of the current standard, which might include changes to SV, but not entertain new enhancements at this time. How short, two years - or what ever would be enough to satisfy the enhancement happy people. (Believe me; I have lots of enhancements ready to go). Dave Rich ________________________________ From: owner-ieee1800@server.eda.org [mailto:owner-ieee1800@server.eda.org] On Behalf Of Bresticker, Shalom Sent: Monday, December 07, 2009 7:45 AM To: Brad Pierce; IEEE 1800 Subject: RE: [P1800] Draft PAR for initial discussion in December 10, 2009 P1800 Meeting Hi, Brad. In Intel, we have had internal discussions, and our DR will present our official position at the meeting. Here are some personal thoughts that do not necessarily reflect the official position of Intel. I would distinguish between Errata and Clarifications. Officially, there are 921 open Mantis items (ignoring those that people have not yet filed). Of those, approximately 525 are classified as Errata (although about 2 dozen are probably SV-BC "Master" parent issues), approximately 210 are Enhancements and 185 Clarifications. SV-AC + SV-SC have 89 issues, SV-BC+1364 have 551, SV-CC has 126, and SV-EC has 155 issues open. While some of the errata have no meaning, I think that probably most of them are worth fixing. On the other hand, with respect to clarifications, I would like to see us identify and emphasize those ambiguities that are known to cause tool portability problems in the real world or are evaluated as likely to do so (most ambiguities on SV-2009 enhancements are future problems, and not current problems). So I would like to see each sub-committee identify those items that should be classified as high priority instead of just working on whatever someone feels like working on. One process that has worked sometimes in the past (and sometimes not) is to have a sub-committee make a small group of people to work on a particular issue by themselves and then bring their work to the entire sub-committee. That requires the group to have a leader who will drive the issue to a conclusion. With respect to IEEE mechanisms, IEEE defines Amendments and Corrigenda: * "Amendment: A document that contains new material to an existing IEEE standard and may contain technical corrections to that standard. * Corrigendum: A document that only contains technical corrections to an existing IEEE standard." "Amendments <http://standards.ieee.org/guides/opman/sect1.html#amendment> and corrigenda <http://standards.ieee.org/guides/opman/sect1.html#corrigenda> are independent projects and are processed with separate PARs and balloted independently in accordance with the requirements of these procedures, including submission to the IEEE-SA Standards Board." An errata sheet is only for editorial errors in the published standard. We bent the rules a little with 1364-2001 Version C and even so, there was a lot of stuff we were not able to put in. Regards, Shalom ________________________________ From: owner-ieee1800@server.eda.org [mailto:owner-ieee1800@server.eda.org] On Behalf Of Brad Pierce Sent: Wednesday, December 02, 2009 10:54 PM To: IEEE 1800 Subject: RE: [P1800] Draft PAR for initial discussion in December 10, 2009 P1800 Meeting Karen, It would be a big help if the 1800 planning discussions could also take into account the issue of Backlog. Clarification/Errata - 1) There is already a lifetime supply of open Mantis issues, and they won't stop flowing in. 2) Resolving them all is not how I want to spend my lifetime. 3) Only a small subset of these are actually seriously impeding SV work. 4) For that small subset, the sooner they are officially resolved, the better. 5) Probably their resolution would go beyond what's allowed in an Errata Sheet. 6) Suppose every subcommittee identified and resolved their top 10 most impeding Mantis issues by this time next year -- is there any IEEE mechanism for officially promulgating them, or would the SV community need to wait until they were incorporated into the next revision standard? Enhancements - 7) It might take more than a lifetime to resolve all of these worthy enhancement ideas. 8) The ones that would make the biggest long-term contribution will also probably require the heaviest lifting. 9) Human nature is to ignore the big stuff, because of the heavy lifting. 10) It would be cool if a "grand challenge" were built in to the process, such as each subcommittee identifying the single enhancement that would have the greatest long-term benefit, then making it happen in the next revision. Thanks for listening, * Brad From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On Behalf Of Karen Pieper Sent: Wednesday, November 18, 2009 3:12 PM To: IEEE 1800 Subject: [P1800] Draft PAR for initial discussion in December 10, 2009 P1800 Meeting Hi, all, Here is a draft of a proposed PAR for our next Revision of the P1800. Please review and be prepared to discuss in our P1800 meeting on December 10, 2009. Please note that the IEEE now requires that what we do be an exact match for what we write in the scope section. Note that items preceded by bullets are intended as discussion points, not recommendations. Please feel free to bring additional ideas. I find having something to poke holes in is easier than a blank sheet of paper. Enjoy! Karen Project Authorization Request (PAR) PAR Request Date: 14 January 2010 PAR Approval Date: PAR Signature Page on File: Type of Project: Revision to IEEE Standard Status: Revision to existing IEEE Standard 1800-2009 Root Project: 1.1 Project No.: P1800 1.2 Type of Document: Standard 1.3 Life Cycle: Full-Use 1.4 Is this document in ballot now? No 2.1 Title Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language Old Title 2.1 Amendment/Corrigenda Title 3.1 Working Group Name SystemVerilog Language Working Group Working Group Chair Pieper, Karen Phone: Email: Working Group Vice Chair Neil Korpusik 3.2 Sponsor IEEE-SA Board of Governors Corporate Advisory Group (BOG/CAG) Sponsor Chair 3.3 Joint Sponsor IEEE Computer Society Design Automation (C/DA) 4.1 Type of Ballot: Entity 4.2 Expected Date of Submission for Initial Sponsor Ballot: June 2013 4.3 Projected Completion Date for Submittal to RevCom: December 2013 5.1 Approximate number of people expected to work on this project: 40 https://spadev.ieee.org/cgi-bin/sadb/par?prttable:1841 (1 of 3)7/31/2006 9:59:44 AM Project Authorization Request (PAR) 5.2 Scope: SystemVerilog 1800 is a Unified Hardware Design, Specification and Verification language; it was approved by the IEEE-SASB in November 2009. This standard creates a new revision of the SystemVerilog 1800 IEEE standard, which includes errata resolutions, clarifications, and enhancements for hardware design and verification, including testbench, checkers, assertions, and coverage. * AMS? This should be added to the scope. That will allow it, if we decide to do it. I would just copy what it said in the "Old Scope" on this topic. Old Scope SystemVerilog 1800 is a Unified Hardware Design, Specification and Verification language. Verilog 1364-2005 is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the Verilog 1364 and SystemVerilog 1800 IEEE standards, which include Errata fixes and resolutions; enhancements; Enhanced assertion language; Merge of Verilog LRM and SystemVerilog 1800 LRM into a single LRM; Integration with AMS; and insures interoperability with other languages such as SystemC and VHDL. 5.3 Is the completion of this document contingent upon the completion of another document? No 5.4 Purpose: The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification language, while resolving Errata and developing enhancements to the current SystemVerilog 1800 IEEE standard. The language is designed to co-exist with and be interoperable with hardware description and verification languages presently used by designers. * A merge of SystemVerilog 1800 with other existing hardware description and verification languages may also occur. Old Purpose: The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving Errata and developing enhancements to current SystemVerilog 1800 IEEE standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers. 5.5 Need for the Project: With the ever increasing complexity of Very Large Scale Integrated Circuit design (VLSI) in the industry as driven by performance, functionality and power tradeoffs, the requirements for an enhanced, more powerful and extensive design language is also increasing. New designs include deeper pipelines, increased logic functionality, complexity, and power issues as well as explosion in the number of lines of Register Transfer Level (RTL) code as a result of low abstraction level of the design supported by the existing languages. This has caused an increase, not only in design complexity, but also in the verification problem. Verification efforts are consuming 60% of the total design cycle and verification gets more challenging when multiple disciplines are used at different stages of the design. Examples of these disciplines are, design specification, assertion based design, test bench based validation, coverage based specifications, and more. SystemVerilog 1800 was developed to enable the use of a unified language for abstract and detailed specification of the design, specification of assertions, coverage, and testbench verification that is based on manual or automatic methodologies. It also offers Application Programming Interfaces (API's) for coverage and assertions, a vendor independent API to access proprietary waveform file formats, and a direct programming interface to access proprietary functionality. This standardization project will further develop the current IEEE standard for SystemVerilog in order to meet the increasing usage of the language as well as enabling consistent tool behavior from different vendors. The new revision of the standard will include resolutions and clarifications to errata and critical enhancements that will enable successful usage of the hardware design and verification language. 5.6 Stakeholders for the Standard: VLSI design and verification engineers as well as the EDA industry. 6.1.a. Has the IEEE-SA policy on intellectual property been presented to those responsible for preparing/submitting this PAR prior to the PAR submittal to the IEEE-SA Standards Board? Yes Presented Date: 2010-01-14 If no, please explain: The policy has been reviewed at every meeting of the Study Group and will be reviewed at all Working Group meetings the first of which will be held after approval of the PAR. 6.1.b. Is the Sponsor aware of any copyright permissions needed for this project? No If yes, please explain: 6.1.c. Is the Sponsor aware of possible registration activity related to this project? No If yes, please explain: 7.1 Are there other standards or projects with a similar scope? Yes If yes, please explain: The scope of this PAR covers portions of the scope of previous PARs submitted by IEEE CS DASC. The existing PARs are: 1076b, 1647, 1666, and 1364. The purpose of this PAR clearly states the intent to co-exist with the results of the standards produced by these Working Groups; to the best of our knowledge there are no impediments at this time to achieve the goal. The work of the 1364 has been completely subsumed by the P1800. In addition Accellera and OSCI (Open SystemC Initiative), both industry consortia within the EDA industry, have done work that covers the area of the scope of this PAR. OSCI with SystemC (a system design language) and Accellera with PSL and OVL, both assertion languages used in the verification of electronic circuit designs. * Do we need to add 1735 Design Intellectual Property (IP) Encryption and Rights Management? * 1801 UPF? Sponsor Organization: IEEE CAG & DASC Project/Standard Number: 1076b, 1647, 1666, 1850 Project/Standard Date: 2013-12-01 Project/Standard Title: IEEE Standard for VHDL, IEEE Standard for 'e' Language, IEEE Standard for SystemC, Accellera Standard for Open Verification Library, IEEE Standard Property Specification Language 7.2 Is there potential for this standard (in part or in whole) to be adopted by another national, regional, or international organization? Yes Technical Committee Name and Number: IEC TC93 WG2 7.3 Will this project result in any health, safety, security, or environmental guidance that affects or applies to human health or safety? No 7.4 Additional Explanatory Notes: 8.1 Sponsor Information: Is the Scope of this project within the approved scope/definition of the Sponsor's Charter? Yes If no, please explain: -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Dec 8 15:03:05 2009
This archive was generated by hypermail 2.1.8 : Tue Dec 08 2009 - 15:03:16 PST