Date: Wed Apr 12 2006 - 11:29:17 PDT
This time it is embedded in the note as I could not send the attached file successfully to our reflector. IEEE-SA STANDARDS BOARD PROJECT AUTHORIZATION REQUEST (PAR) FORM - 2006 The submittal deadlines for the Year 2006 are available. Prior to submitting your PAR, please review the NesCom Conventions. 1. ASSIGNED PROJECT NUMBER P (Please leave blank if not available.) 2. SPONSOR DATE OF REQUEST Day: Month: Year: 2006 3. TYPE OF DOCUMENT (Please check one.) Standard forRecommended Practice for {document stressing the verb "should"} Guide for {document in which good practices are suggested, stressing the verb "may"} 4. TITLE OF DOCUMENT Draft 5. LIFE CYCLE Full-Use Trial-Use 6. TYPE OF PROJECT New document Revision of an existing document (indicate number and year existing document was published in box to the right): (Nov-08-2005) Amendment to an existing document (indicate number and year existing document was published in box to the right): Corrigendum to an existing document (indicate number and year existing document was published in box to the right): Modified PAR (indicate PAR Number and Approval Date here: P Day Month Year ) Is this project in ballot now? Yes No State reason for modifying the PAR in Item #19. 7. WORKING GROUP INFORMATION: Name of Working Group: Approximate Number of Expected Working Group Members: 8. CONTACT INFORMATION FOR WORKING GROUP CHAIR (must be an IEEE-SA member as well as an IEEE and/or Affiliate Member) Name of Working Group Chair: First Name: Last Name: Telephone: FAX: E-mail: 9. CONTACT INFORMATION FOR CO-CHAIR/OFFICIAL REPORTER, Project Editor or Document Custodian if different from the Working Group Chair (must be an IEEE-SA member as well as an IEEE and/or Affiliate Member) Name of Co-Chair/Official Reporter (if different than Working Group Chair ): First Name: Last Name: Telephone: FAX: E-mail: 10. CONTACT INFORMATION FOR SPONSORING SOCIETY OR STANDARDS COORDINATING COMMITTEE Sponsoring Society and Committee: (Please choose the correct acronym for your Sponsor Society/Technical Committee or SCC. For an acronym list, please click here.) Sponsor Committee Chair: First Name: Last Name: Telephone: FAX: E-mail: Standards Coordinator (Power Engineering Society Only): Standards Coordinator: First Name: Last Name: Telephone: FAX: E-mail: IF THIS PROJECT IS BEING SPONSORED BY TWO SPONSORS, PLEASE COMPLETE THE INFORMATION BELOW Sponsoring Society and Committee: (Please choose the correct acronym for your Sponsor Society/Technical Committee or SCC. For an acronym list, please click here.) Sponsor Committee Chair: First Name: Last Name: Telephone: FAX: E-mail: Standards Coordinator (Power Engineering Society Only): Standards Coordinator: First Name: Last Name: Telephone: FAX: E-mail: 11. SPONSOR BALLOTING INFORMATION (Please choose one of the following): Individual Balloting Entity Balloting Mixed Balloting (combination of Individual and Entity Balloting) Expected Date of Submission for Initial Sponsor Ballot: Day: Month: Year: Please review the PAR form three months prior to submitting your draft for ballot to ensure that the title, scope, and purpose on the PAR form match the title, scope, and purpose on the draft. If they do not match, you will probably need to submit a modified PAR. Additional communication and input from other organizations or other IEEE Standards Sponsors should be encouraged through participation in the working group or the invitation pool. 12. PROJECTED COMPLETION DATE FOR SUBMITTAL TO REVCOM Day: Month: Year: If this is a MODIFIED PAR and the completion date is being extended past the original four-year life of the PAR, please answer the following questions. If this is not a modified PAR, please go to Question #13. a. Statement of why the extension is required: b. When did work on the first draft begin? Day: Month: Year: c. How many people are actively working on the project? d. How many times a year does the working group meet in person? e. How many times a year does the working group meet using electronic means (i.e., teleconference, e-mail, web-based meetings)? f. How frequently is a draft version circulated to the working group? g. How much of the Draft is stable (Format: NN%)? % h. How many significant working revisions has the Draft been through? i. Briefly describe what the development group has already accomplished, and what remains to be done. 13. SCOPE OF PROPOSED PROJECT Please detail the projected output including technical boundaries. Please be brief (less than 5 lines). SystemVerilog 1800 is a Unified Hardware Design, Specification and Verification language. Verilog 1364-2005 is a design language. Both standards were approved by the IEEE-SASB in November 2005. The proposed project will create new revisions of the Verilog 1364 and SystemVerilog 1800 IEEE standards which will include Errata fixes and resolutions; enhancements; Enhanced assertion language; Merge of the 1364 Verilog LRM and SystemVerilog 1800 LRM into a single LRM ; Integration with AMS; and interoperability with other languages such as SystemC and VHDL FOR REVISED DOCUMENTS ONLY - Please detail the projected output including the scope of the original document, amendments, and additions. Is the completion of this document contingent upon the completion of another document? Yes (with detailed explanation below) No 14. PURPOSE OF PROPOSED PROJECT Please clearly and concisely define "why" the document is being done. Please be brief (less than 5 lines). The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving Errata and developing enhancements to current SystemVerilog 1800 IEEE standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers. FOR REVISED DOCUMENTS ONLY - Please include the purpose of the original document and the reason for the document's revision. 14a. Please give the specific reason for the standardization project, with particular emphasis on the problem being solved, the benefit to be received and target users or industries. With the ever increasing complexity of Very Large Scale Integrated Circuit design (VLSI) in the industry as driven by performance, functionality and power tradeoffs, the requirements for an enhanced, more powerful and extensive design language is also increasing. New designs include deeper pipelines, increased logic functionality, complexity, and power issues as well as explosion in the number of lines of Register Transfer Level (RTL) code as a result of low abstraction level of the design supported by the existing languages. This has caused an increase, not only in design complexity, but also in the verification problem. Verification efforts are consuming 60% of the total design cycle and verification gets more challenging when multiple disciplines are used at different stages of the design. Examples of these disciplines are, design specification, assertion based design, test bench based validation, coverage based specifications, and more. SystemVerilog 1800 was developed to enable the use of a unified language for abstract and detailed specification of the design, specification of assertions, coverage, and test bench verification that is based on manual or automatic methodologies. It also offers Application Programming Interfaces (API’s) for coverage and assertions, a vendor independent API to access proprietary waveform file formats, and a direct programming interface to access proprietary functionality. This standardization project will further develop the current IEEE standard for SystemVerilog in order to meet the increasing usage of the language as well as enabling consistent tool behavior from different vendors. The new revision of the standard will include resolutions and clarifications to Errata and critical enhancements that will enable successful usage of the hardware design and verification language. Furthermore, and as SystemVerilog is a superset of Verilog, the new revision will merge with Verilog 1364-2005 standard to ensure a single reference manual for users and EDA vendors alike. The new standard will also enable interoperability with existing languages such as VHDL and SystemC, as well as integration w/ Analog Mixed Signal (AMS). 15. INTELLECTUAL PROPERTY (Please answer each of the questions below) Has the Sponsor reviewed the IEEE-SA patent material with the working group? Yes No Is the Sponsor aware of copyright permissions needed for this project? Yes No If yes, please explain: Is the Sponsor aware of trademarks that apply to this project? Yes No If yes, please explain: Is the Sponsor aware of possible registration of objects or numbers to be included in or used by this project? Yes No If yes, please explain: 16. ARE THERE OTHER DOCUMENTS OR PROJECTS WITH A SIMILAR SCOPE? Yes (with detailed explanation below) No If Yes, please answer the following: Sponsor Organization: Project Number: Project Date: Day: Month: Year: Project Title: 17. FUTURE ADOPTIONS Is there potential for this document (in part or in whole) to be adopted by another national, regional or international organization? If Yes, the following questions must be answered: Technical Committee Name and Number: TC SC WG Other Organization Contact Information: Contact Name: First Name: Last Name: Contact Telephone Number: Contact FAX Number: Contact E-mail address: 18. IF THE PROJECT WILL RESULT IN ANY HEALTH, SAFETY, OR ENVIRONMENTAL GUIDANCE THAT AFFECTS OR APPLIES TO HUMAN HEALTH OR SAFETY, PLEASE EXPLAIN IN FIVE SENTENCES OR LESS. 19.ADDITIONAL EXPLANATORY NOTES (Item Number and Explanation) I acknowledge having read and understood the IEEE Code of Ethics. I agree to conduct myself in a manner that adheres to the IEEE Code of Ethics when engaged in official IEEE business. The PAR Copyright Release and Signature Page must be submitted by FAX to +1 732-875-0695 to the NesCom Administrator before this PAR will be forwarded to NesCom and the Standards Board for approval. Regards, --- Johny. ----- Forwarded by Johny Srouji/Austin/IBM on 04/11/2006 07:14 PM ----- Johny Srouji/Austin/IBM 04/11/2006 07:03 PM To IEEE P1800 cc Subject modified PAR Hi All, Here is the PAR which we reviewed and modified in our tele-call meeting last week. I am waiting for Steve to send me the minutes for review and capturing other changes I may have missed. Regards, --- Johny.