Re: [P1800] Re:

We'll check on how we get this fixed in the next draft. I'll make sure to 
have an agenda item in our next WG meeting for several fixes which may 
need to be made, pending approval of the WG. This would be one of them. As 
the chair of the WG, I want to make sure that we acknowledge all those who 
made significant and valuable contributions.

Regards,

--- Johny.





Charles Dawson <chas@cadence.com> 
Sent by: owner-ieee1800@eda.org
09/16/2005 01:35 PM
Please respond to
chas


To
Arturo Salz <Arturo.Salz@synopsys.com>, IEEE1800 <ieee1800@eda.org>
cc
Ghassan Khoory <Ghassan.Khoory@synopsys.com>, stuart@sutherland.com, 
Tapati Basu <Tapati.Basu@synopsys.com>, Oz.Levia@synopsys.com
Subject
[P1800] Re:






Hi Arturo,

Yes, Tapati did a great deal of work on the standard.  This is undoubtedly
an oversight.  I'm sending this to the p1800 committee, who can hopefully
correct it.

   -Chas


Arturo Salz wrote:
> Charles, Ghasan, Stu,
> 
> 
> 
> I just received the attached message from Tapati Basu.
> 
> Tapati was an active member of the CC committee (she had voting rights 
> as indicated by http://www.eda-twiki.org/sv-cc/hm/2771.html ), unfortunately, 
> her name does not appear in the standard.
> 
> I?m certain that this is just an unintentional omission that I hope we 
> can correct before the standard is published.
> 
> Thanks.
> 
> 
> 
>             Arturo
> 
> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------
> 
> Subject:
> System verilog LRM
> From:
> "Tapati Basu" <tbasu@synopsys.com>
> Date:
> Fri, 16 Sep 2005 10:08:04 -0700
> To:
> "Ashish Naik" <ashish@synopsys.com>, "Arturo Salz" <salz@synopsys.com>, 
> "Rohit Vora" <rohit@synopsys.com>, "Surrendra Dudani" 
<dudani@synopsys.com>
> 
> 
> Hi Surrendra/Arturo,
> 
> 
> I hope everyone knows that I worked almost single handedly (of course 
> Joao and Alok was
> helping me a lot) to specify all of SV-VPI. I had to draw all diagrams 
> by hand and sent them
> to our doc guys for making pdf versions.  Even Draft3.a had all my 
> examples and all my diagrams.
> Worked along with Sachi to fix the errata and attended long 5 hour 
> meetings.
> 
> But when the final draft came out, I can not see my name anywhere in the 

> LRM but all other
> Synopsys names are there. Isn't this demotivating ???  Is it that 
> because for the final phase
> Sachi represented Synopsys ? But then why I was called for those painful 

> meetings and worked
> Day and night to fix those erratas ? Can I assume that all my hard work 
> was just in vain ?
> 
> Hope someone can explain me.
> 
> - Thanks,
> Tapati
> 


-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com