Hi:
SystemVerilog Working Group. I took this from the P1364 PAR.
Thanks,
Noelle
-- Noelle D. Humenick Coordinating Program Manager IEEE Standards n.humenick@ieee.org PH: +1 732 562 3818; FX: +1 732 562 1571 http://standards.ieee.org/ The Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331 USA *************************************** Shalom.Bresticker@fr eescale.com To: ieee1800@eda.org Sent by: cc: owner-ieee1800@eda.o Subject: [P1800] 1364 title page rg 01/23/2005 10:45 AM Please respond to Shalom.Bresticker On the title page of the 1364 lrm, I have to put the name of the WG which prepared it. What is the name? Thanks, Shalom -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Sun Jan 23 07:52:06 2005
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