Re: 11 October 2004 Unapproved Meeting Minutes

Thanks.

So, by what date do ETF and BTF have to approve their changes?

Shalom

"Srouji, Johny" wrote:

> Hi Shalom,
>
> The "spirit" of the discussion was that we need to sync-up between IEEE
> versions of SystemVerilog and Verilog LRM. Our schedule is driven by one
> of the major milestones, and that's Feb 1st. By this8 date we would like
> to have the 2nd draft of IEEE SystemVerilog LRM completed. This implies
> that we need to complete issues resolution for this draft in December
> (no later than mid month).
>
> Hope this clarifies. We will make sure the minutes clarify this as well.
>
> Thanks,
>
> --- Johny.
>
> -----Original Message-----
> From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On Behalf
> Of Shalom.Bresticker@freescale.com
> Sent: Monday, October 18, 2004 6:22 PM
> To: Brophy, Dennis
> Cc: ieee1800@eda.org
> Subject: Re: 11 October 2004 Unapproved Meeting Minutes
>
> According to Karen Pieper, the deadline for 1364 was maintained as
> December 2004.
> If so, the minutes are misleading. The last sentence on that subject in
> the
> minutes is
>
> > After discussion, it was noted that a March 2005 cutoff would permit
> us to
> > meet the DAC completion timeline.
>
> Shalom
>
> On Thu, 14 Oct 2004 Shalom.Bresticker@freescale.com wrote:
>
> > Thank you.
> >
> > But something is still not clear.
> >
> > > The timeline that we are working off of is the basis to determine
> slack
> > > and schedule issues like the cutoff date. If we were to go past the
> > > date we would need to revisit the timeline.
> >
> > Thank you, I understand that.
> > But I repeat my original question:
> >
> > > "The question was raised as to when the cutoff for work would need
> to
> > > be. Would it need to be December 2004 or could it be March 2005?
> After
> > > discussion, it was noted that a March 2005 cutoff would permit us to
> > > meet the DAC completion timeline."
> > >
> > > Was a decision made?
> >
> > The minutes say there was a discussion and it was "noted that ...".
> > The minutes do NOT say that the group DECIDED to set a cutoff of March
> > instead of December for the ETF/BTF work.
> >
> > The question is, when ETF and BTF plan their work, can they assume
> they
> > have until March to finish or not?
> >
> > Also, does "March" mean March 1 or March 31?
> >
> > Sorry if it sounds picky, but it is still ambiguous, and of
> non-trivial
> > importance.
> >
> > Thanks,
> > Shalom
> >
> >
>
> --
> Shalom Bresticker Shalom.Bresticker
> @freescale.com
> Design & Verification Methodology Tel: +972 9
> 9522268
> Freescale Semiconductor Israel, Ltd. Fax: +972 9
> 9522890
> POB 2208, Herzlia 46120, ISRAEL Cell: +972 50
> 5441478
>
> [ ]Freescale Internal Use Only [ ]Freescale Confidential
> Proprietary

--
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478
[ ]Freescale Internal Use Only      [ ]Freescale Confidential Proprietary