RE: PatCom update

Johny,

In view of the limitation of the LOA form that is available from IEEE
PatCom we have prepared a LOA that Cadence will sign and submit to P1800
and PatCom that supports our non-assertion position with respect to all
SystemVerilog related patents. We recommend that this same agreement
be signed by all other participants.

Regards,

  Victor

________________________________

From: Srouji, Johny [mailto:johny.srouji@intel.com]
Sent: Thursday, September 09, 2004 7:17 AM
To: Victor Berman
Subject: RE: PatCom update

Yes, and it is actually reflected in the updated action items (I think
the links are not working properly - sent a note to Dennis).

Attached are few files which will probably answer your question. We
shall discuss this in our WG F2F. Let me know if this answers your
question.

See you,

--- Johny.

________________________________

From: Victor Berman [mailto:vberman@cadence.com]
Sent: Thursday, September 09, 2004 2:09 PM
To: Srouji, Johny
Subject: PatCom update

Johny,

Have you had a chance to talk to PatCom about the patent issues in the
WG? I would like to try to move this along quickly so that we can come
to an agreement on the next steps.

Regards,

 Victor

Victor Berman

Group Director

Industry Marketing

Tel: 978 262 6560

Mobile: 978 884 5113

vberman@cadence.com