SystemVerilog IEEE 1800 Standardization Activity: RE: Call for n

From: David W. Smith <dwsmith@synopsys.com>
Date: Mon Jul 19 2004 - 11:38:05 PDT

The access to the database used for sv is not limited to Accellera. There
was a process decision that the SV database would only create accounts for
people that were part of Accellera. This could easily be amended.

Regards
David Smith

-----Original Message-----
From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On Behalf Of
Michael McNamara
Sent: Monday, July 19, 2004 9:11 AM
To: Srouji, Johny
Cc: Eugene Zhang; Jay Lawrence; ieee1800@eda.org
Subject: RE: Call for nomination

I believe the issue is that only Accellera member companies can submit
bugs to the Accellera database, and that Jeda is not an Accellera
company.

Let me be clear - for start up reasons, it is great that Accellera is
helping faciliate things. As an Accellera member, I am proud of us.

However it would seem logical that P1800 is the sole ownerof its own
database for its specification very soon now. It would be wonderful
if Accellera offers to support and faciliate the P1800 database of
errata for the long term; and starts the process by transfering the
existing database to P1800. However, P1800, operating under the rules
of IEEE_CAG & IEEE_DASC, and all of that hierarchy must be the
organization that sets the rules for access to the database.

-mac
P1800 member

-- On Jul 18 2004 at 18:54, Srouji, Johny sent a message:
> To: eugene@jedatechnologies.com, lawrence@cadence.com, ieee1800@eda.org
> Subject: "RE: Call for nomination"
> Eugene,
>
> Please submit SystemVerilog Errata that you have found to the relevant
> technical committees for design (sv-bc), test Bench extensions (sv-ec),
> Assertions (sv-ac) or C-Interface (sv-cc), based on the type of Errata.
>
>
>
> Thanks,
>
>
>
> --- Johny.
>
>
>
> ________________________________
>
> From: Eugene Zhang [mailto:eugene@jedatechnologies.com]
> Sent: Friday, July 16, 2004 10:04 PM
> To: Srouji, Johny; 'Jay Lawrence'; ieee1800@eda.org
> Subject: RE: Call for nomination
>
>
>
> Hi all,
>
>
>
> Jeda would like to submit some erratta ( syntax errors, for instance)
> and hope we can quickly reach a conclusion and
>
> decide an official mechanism for such feedbacks and fixes.
>
>
>
> -Eugene
>
> -----Original Message-----
> From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On
> Behalf Of Srouji, Johny
> Sent: Friday, July 16, 2004 5:48 AM
> To: Jay Lawrence; ieee1800@eda.org
> Subject: RE: Call for nomination
>
> I want one person to come to P1800 and present the collective
> Errata from all 4 sub-committees. He will bring the recommendations
> which will be ratified in the P1800 WG.
>
> I suggest that you talk to Victor Berman from Cadence regarding
> this as he was present in the meeting where we discussed this.
>
>
>
> Thanks,
>
>
>
> --- Johny.
>
>
>
>
> ________________________________
>
>
> From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On
> Behalf Of Jay Lawrence
> Sent: Friday, July 16, 2004 3:14 PM
> To: ieee1800@eda.org
> Subject: RE: Call for nomination
>
>
>
> Johny,
>
>
>
> I personally find it difficult to nominate individuals for a
> position that does not as yet have a definition.
>
>
>
> What are the responsibilities of this position?
>
>
>
> As you know, within the SystemVerilog world in Accellera we
> really have 4 erratta committees; design, testbench, assertions, and 'C'
> interfaces.
>
>
>
> Why aren't we preserving each of these 4 groups instead of
> having one erratta group which will in turn then be hierarchical?
>
>
>
> Jay
>
>
>
>
>
> ===================================
> Jay Lawrence
> Senior Architect
> Functional Verification
> Cadence Design Systems, Inc.
> (978) 262-6294
> lawrence@cadence.com
> ===================================
>
>
>
>
>
>
> ________________________________
>
>
> From: owner-ieee1800@eda.org
> [mailto:owner-ieee1800@eda.org] On Behalf Of Srouji, Johny
> Sent: Tuesday, July 13, 2004 3:42 PM
> To: ieee1800@eda.org
> Subject: FW: Call for nomination
>
> I am submitting this to the reflector. Please note the
> deadline is July 22nd.
>
>
>
>
> ________________________________
>
>
> From: Srouji, Johny
> Sent: Thursday, July 08, 2004 7:52 PM
> To: Dennis Brophy; Vassilios.Gerousis@infineon.com;
> Oz.Levia@synopsys.com; mac@verisity.com; Hans Zander; Yaron Wolfsthal;
> vberman@cadence.com; steve_mills@hp.com; Peter Ashenden; Shrenik Mehta
> (shrenik.mehta@Sun.COM); Neil.Korpusik@Sun.COM; Clifford E. Cummings;
> steve_mills@hp.com; wolfgang.ecker@infineon.com
> Cc: Srouji, Johny; e.rashba@ieee.org; Peter Ashenden
> Subject: Call for nomination
>
>
>
> Dear Colleague:
>
> According to our F2F meeting minutes on July 1st, the
> following motion was made: "Move Accellera SystemVerilog technical
> subcommittees to IEEE P1800 Errata Technical Sub-Working Group". This
> motion was unanimously approved.
>
>
>
> This was followed by a motion to temporarily appoint
> Vassilios Gerousis as the chair of the Errata Technical Sub-Working
> Group. As a chair of the P1800 WG, I got the action item to initiate the
> process of a call for nominations for the permanent Errata Technical
> Sub-Working Group Chair. This motion was unanimously approved.
>
>
>
> Therefore, I am sending this note to initiate the call
> for nominations for the permanent Errata Technical Sub-Working Group
> Chair. Please send me your nominations within 14 days (by July the 22nd
> at the latest). Once nominations are done, I will initiate the voting
> process which will also last for 14 days.
>
>
>
> Please send me your nominations directly to my account.
>
>
>
> Thanks for your cooperation,
>
>
>
> --- Johny.
>
>
>
>
>
>
>
>
>
> <html>
>
> <head>
> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii">
> <meta name=Generator content="Microsoft Word 11 (filtered)">
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> <style>
> 
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>
> <div class=Section1>
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans
MS";color:green'>Eugene size=2 color=green face="Comic Sans MS"> font-family:"Comic Sans MS";color:green'>,
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans MS";color:green'>Please
submit
> SystemVerilog Errata that you have found to the relevant technical
committees
> for design (sv-bc), test Bench extensions (sv-ec), Assertions (sv-ac) or
C-Interface
> (sv-cc), based on the type of Errata.
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans
MS";color:green'> 
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans
MS";color:green'>Thanks,
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans
MS";color:green'> 
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans MS";color:green'>---
Johny.
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans
MS";color:green'> 
>
> <div>
>
> <div class=MsoNormal align=center style='text-align:center'> face="Times New Roman">
>
> <hr size=2 width="100%" align=center tabindex=-1>
>
> </div>
>
> <span
style='font-size:10.0pt;
> font-family:Tahoma;font-weight:bold'>From: face=Tahoma> Eugene
Zhang
> [mailto:eugene@jedatechnologies.com] 
> Sent: Friday, July 16, 2004
10:04
> PM 
> To: Srouji, Johny; 'Jay
Lawrence';
> ieee1800@eda.org 
> Subject: RE: Call for
nomination
>
> </div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> <div>
>
> font-family:Arial'>Hi all,
>
> </div>
>
> <div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> </div>
>
> <div>
>
> font-family:Arial'>Jeda would like to submit some erratta ( syntax
errors,
> for instance) and hope we can quickly reach a conclusion
and
>
> </div>
>
> <div>
>
> font-family:Arial'>decide an official mechanism for such feedbacks and
fixes.
>
> </div>
>
> <div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> </div>
>
> <div>
>
> font-family:Arial'>-Eugene
>
> </div>
>
> <blockquote
style='margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>
>
> style='font-size:10.0pt;font-family:Tahoma'>-----Original
Message----- 
> From: owner-ieee1800@eda.org
> [mailto:owner-ieee1800@eda.org] On
Behalf Of Srouji,
> Johny 
> Sent: Friday, July 16, 2004
5:48
> AM 
> To: Jay Lawrence;
ieee1800@eda.org 
> Subject: RE: Call for
nomination
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans MS";color:green'>I want
one
> person to come to P1800 and present the collective Errata from all 4
> sub-committees. He will bring the recommendations which will be ratified
in the
> P1800 WG.
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans MS";color:green'>I
suggest that
> you talk to Victor Berman from Cadence regarding this as he was present
in the
> meeting where we discussed this.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans
MS";color:green'>Thanks,
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans MS";color:green'>---
Johny. 
>
> <span
style='font-size:
> 12.0pt'> 
>
> <div>
>
> <div class=MsoNormal align=center style='text-align:center'> face="Times New Roman">
>
> <hr size=2 width="100%" align=center tabIndex=-1>
>
> </div>
>
> <span
style='font-size:10.0pt;
> font-family:Tahoma;font-weight:bold'>From: face=Tahoma>
> owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] <span
> style='font-weight:bold'>On Behalf Of Jay Lawrence 
> Sent: Friday, July 16, 2004
3:14
> PM 
> To: ieee1800@eda.org 
> Subject: RE: Call for
nomination
>
> </div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Arial'>Johny,
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Arial'>I personally find it difficult to nominate individuals
for a
> position that does not as yet have a definition.
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Arial'>What are the responsibilities of this
position?
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Arial'>As you know, within the SystemVerilog world in
Accellera we
> really have 4 erratta committees; design, testbench, assertions, and 'C'
> interfaces.
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Arial'>Why aren't we preserving each of these 4 groups
instead of
> having one erratta group which will in turn then be
hierarchical?
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Arial'>Jay
>
> <div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> </div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:10.0pt'>=================================== 
> Jay Lawrence 
> Senior Architect 
> Functional Verification 
> Cadence Design Systems, Inc. 
> (978) 262-6294 
> lawrence@cadence.com 
> =================================== 
>
> <div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> </div>
>
> <blockquote style='border:none;border-left:solid black 1.5pt;padding:0in
0in 0in 4.0pt;
>
margin-left:3.75pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>
>
> <span
style='font-size:
> 12.0pt'> 
>
> <div class=MsoNormal align=center style='text-align:center'> face="Times New Roman">
>
> <hr size=2 width="100%" align=center tabIndex=-1>
>
> </div>
>
> 
style='font-size:10.0pt;font-family:Tahoma;font-weight:bold'>From:</f
ont> size=2 face=Tahoma>
> owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] <span
> style='font-weight:bold'>On Behalf Of Srouji, Johny 
> Sent: Tuesday, July 13, 2004
3:42
> PM 
> To: ieee1800@eda.org 
> Subject: FW: Call for
nomination
>
> <span
> style='font-size:10.0pt;font-family:"Comic Sans MS";color:green'>I am
submitting
> this to the reflector. Please note the deadline is July
22nd.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <div>
>
> <div class=MsoNormal align=center style='text-align:center'> face="Times New Roman">
>
> <hr size=2 width="100%" align=center tabIndex=-1>
>
> </div>
>
> <span
style='font-size:10.0pt;
> font-family:Tahoma;font-weight:bold'>From: face=Tahoma> Srouji,
Johny 
> Sent: Thursday, July 08,
2004 7:52
> PM 
> To: Dennis Brophy;
> Vassilios.Gerousis@infineon.com; Oz.Levia@synopsys.com; mac@verisity.com;
Hans Zander; Yaron Wolfsthal; vberman@cadence.com; steve_mills@hp.com; Peter
Ashenden; Shrenik
> Mehta (shrenik.mehta@Sun.COM); Neil.Korpusik@Sun.COM; Clifford E.
Cummings; steve_mills@hp.com; wolfgang.ecker@infineon.com 
> Cc: Srouji, Johny;
> e.rashba@ieee.org; Peter Ashenden 
> Subject: Call for
nomination
>
> </div>
>
> <span
style='font-size:
> 12.0pt'> 
>
> font-family:Verdana;color:navy'>Dear Colleague:
>
> <span
style='font-size:
> 10.0pt;font-family:Verdana;color:navy'>According to our F2F meeting
minutes on
> July 1st, the following motion was made: “Move Accellera
> SystemVerilog technical subcommittees to IEEE P1800 Errata Technical
> Sub-Working Group”.  This motion was unanimously
approved.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 10.0pt;font-family:Verdana;color:navy'>This was followed by a motion to
> temporarily appoint Vassilios Gerousis as the chair of the Errata
Technical
> Sub-Working Group. As a chair of the P1800 WG, I got the action item to
> initiate the process of a call for nominations for the permanent Errata
> Technical Sub-Working Group Chair.  This motion was unanimously
approved.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 10.0pt;font-family:Verdana;color:navy'>Therefore, I am sending this note
to initiate
> the call for nominations for the permanent Errata Technical Sub-Working
Group
> Chair. Please send me your nominations within 14 days (by
 style='font-weight:bold'>July the 22nd at the latest). Once
> nominations are done, I will initiate the voting process which will also
last
> for 14 days.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 10.0pt;font-family:Verdana;color:navy'>Please send me your nominations
directly
> to my account.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 10.0pt;font-family:Verdana;color:navy'>Thanks for your
cooperation,
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 10.0pt;font-family:Verdana;color:navy'>--- Johny.
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 12.0pt'> 
>
> <span
style='font-size:
> 12.0pt'> 
>
> </blockquote>
>
> </blockquote>
>
> </div>
>
> </body>
>
> </html>
Received on Mon Jul 19 11:39:19 2004

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