Eugene,
Please submit SystemVerilog Errata that you have found to the relevant
technical committees for design (sv-bc), test Bench extensions (sv-ec),
Assertions (sv-ac) or C-Interface (sv-cc), based on the type of Errata.
Thanks,
--- Johny.
________________________________
From: Eugene Zhang [mailto:eugene@jedatechnologies.com]
Sent: Friday, July 16, 2004 10:04 PM
To: Srouji, Johny; 'Jay Lawrence'; ieee1800@eda.org
Subject: RE: Call for nomination
Hi all,
Jeda would like to submit some erratta ( syntax errors, for instance)
and hope we can quickly reach a conclusion and
decide an official mechanism for such feedbacks and fixes.
-Eugene
-----Original Message-----
From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On
Behalf Of Srouji, Johny
Sent: Friday, July 16, 2004 5:48 AM
To: Jay Lawrence; ieee1800@eda.org
Subject: RE: Call for nomination
I want one person to come to P1800 and present the collective
Errata from all 4 sub-committees. He will bring the recommendations
which will be ratified in the P1800 WG.
I suggest that you talk to Victor Berman from Cadence regarding
this as he was present in the meeting where we discussed this.
Thanks,
--- Johny.
________________________________
From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On
Behalf Of Jay Lawrence
Sent: Friday, July 16, 2004 3:14 PM
To: ieee1800@eda.org
Subject: RE: Call for nomination
Johny,
I personally find it difficult to nominate individuals for a
position that does not as yet have a definition.
What are the responsibilities of this position?
As you know, within the SystemVerilog world in Accellera we
really have 4 erratta committees; design, testbench, assertions, and 'C'
interfaces.
Why aren't we preserving each of these 4 groups instead of
having one erratta group which will in turn then be hierarchical?
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
________________________________
From: owner-ieee1800@eda.org
[mailto:owner-ieee1800@eda.org] On Behalf Of Srouji, Johny
Sent: Tuesday, July 13, 2004 3:42 PM
To: ieee1800@eda.org
Subject: FW: Call for nomination
I am submitting this to the reflector. Please note the
deadline is July 22nd.
________________________________
From: Srouji, Johny
Sent: Thursday, July 08, 2004 7:52 PM
To: Dennis Brophy; Vassilios.Gerousis@infineon.com;
Oz.Levia@synopsys.com; mac@verisity.com; Hans Zander; Yaron Wolfsthal;
vberman@cadence.com; steve_mills@hp.com; Peter Ashenden; Shrenik Mehta
(shrenik.mehta@Sun.COM); Neil.Korpusik@Sun.COM; Clifford E. Cummings;
steve_mills@hp.com; wolfgang.ecker@infineon.com
Cc: Srouji, Johny; e.rashba@ieee.org; Peter Ashenden
Subject: Call for nomination
Dear Colleague:
According to our F2F meeting minutes on July 1st, the
following motion was made: "Move Accellera SystemVerilog technical
subcommittees to IEEE P1800 Errata Technical Sub-Working Group". This
motion was unanimously approved.
This was followed by a motion to temporarily appoint
Vassilios Gerousis as the chair of the Errata Technical Sub-Working
Group. As a chair of the P1800 WG, I got the action item to initiate the
process of a call for nominations for the permanent Errata Technical
Sub-Working Group Chair. This motion was unanimously approved.
Therefore, I am sending this note to initiate the call
for nominations for the permanent Errata Technical Sub-Working Group
Chair. Please send me your nominations within 14 days (by July the 22nd
at the latest). Once nominations are done, I will initiate the voting
process which will also last for 14 days.
Please send me your nominations directly to my account.
Thanks for your cooperation,
--- Johny.
Received on Sun Jul 18 08:54:49 2004
This archive was generated by hypermail 2.1.8 : Sun Jul 18 2004 - 08:54:51 PDT