System Verilog
LRM Changes to Draft 5
On
Status Legend: Open, Remove Note, Change, No Change
ID	Committee	Section	Description	Status	Changes
LRM-253	SV-BC	15.12	Typo in clock-domain from Cliff's review	Change	Section 15.12
LRM-254	SV-BC	9.1 9.7	Remove references to test-and-set per Arturo and Dave Rich	Change	Section 9.1 Section 9.7
LRM-255	SV-CC	26.1.2	Included change based on request from Joao and Arturo	Change	Section 26.1.2
LRM-256	SV-EC	3.3.1	Correction to integral type definition from Arturo	Change	Section 3.3.1
LRM-257	SV-EC	12.4.8	Change integral singular to integral per Arturo	Change	Section 12.4.8