Subject: Re: [sv-ec] Event Proposal
From: "Arturo Salz" <[email-masked]>
To: <[email-masked]>
Date: Mon, 10 Mar 2003 10:17:03 -0800

Francoise,

Thanks for the comments.

The $wait_all and $wait_any and $wait_order are shorthand notations for the following:

$wait_all( a, b, c )

    fork
        wait( a.triggered ); wait( b.triggered ); wait( c.triggered ); 
    join

$wait_any( a, b, c )

    wait( a.triggered || b.triggered || c.triggered );

$wait_order( a, b, c )

    reg  abc[1:3] = '0;
    fork
        begin wait( a.triggered ); abc[1] = 1; if( abc != '100 ) $error; end
        begin @b; abc[2] = 1; if( abc != '110 ) $error; end
        begin @c; abc[3] = 1; if( abc != '111 ) $error; end
    join_none

As for enhancing the other operators, that approach seemed to be rather
controversial and we were unable to reach consensus. I'd prefer to keep
the enhancement simple so that we can all agree.

    Arturo

----- Original Message ----- 
From: "Francoise Martinolle" <[email-masked]>
To: "Arturo Salz" <[email-masked]>
Cc: <[email-masked]>
Sent: Monday, March 10, 2003 8:07 AM
Subject: Re: [sv-ec] Event Proposal

Arturo,

I like this proposal better.
I suggest that for clarification the definition of $wait_all and $wait_any, 
$wait_order,
is also described in terms of semantically equivalent verilog code.

Note: I am not sure if I have the correct equivalent description. But this 
is just provided
as an example.
Ex:
$wait_all(a, b);
<stmt>;
creates a single process equivalent to:

equivalent to:
                        rega = 1'b0;  initialize the state of a and b
                        regb = 1'b0;

                        initial(@a or @b)
                          if (a.triggered)
                              rega = 1'b1;// state that a has triggered 
already once
                          if (a.triggered) || (rega == 1'b1)  { // a 
triggered now or has triggered before
                              @b;
                          }
                          if (b.triggered)
                              regb = 1'b1;// state that b has triggered 
already once
                          if ((b.triggered) || (regb == 1'b1))
                              @a;
                          <stmt>
                          rega = 1'b0; // reset rega and regb
                          regb = 1'b0;
                        end

$wait_any(a,b);
<stmt>;
creates a single process equivalent to
                  @(a or b) <stmt>;

$wait_order(a, b);
<stmt>
creates a single process equivalent to:
                       rega = 1'b0;
                       initial  (@a or @b)
                          if (a.triggered) {
                                rega = 1'b1;
                                @b;
                               <stmt>

                          }
                          if (b.triggered && (!rega))
                             error;

                       end

I also think that another alternative is to enhance the wait statement 
defined in section 9.7.6
in the Verilog 1364 LRM instead of introducing new built in system tasks

For example:
    wait (@a or @b); would wait on either a or b events to trigger;
                              equivalent to $wait_any(a, b)
    wait ((@a or a.triggered) and (@b or b.triggered)); would wait on both 
a and b events to
                                                                            trigger 
in any order ;
    In order to wait across multiple simulation steps, you have to 
introduce a new operator to
    tell you that the execution will not continue until the condition 
expression "until" becomes
   true. The wait statement waits for the first condition expression to 
become true and
   then blocks again until the until expression becomes true.

    wait ((@a and @b) or (@a until b.triggered) or ( (@b until a.triggered));
                                                                            equivalent 
to $wait_all(a, b)

    wait (@a);
    wait (@b): would wait on a event to trigger then b event to trigger;
                    equivalent to $wait_order(a, b);

Francoise
        '

At 04:25 PM 3/7/2003 -0800, Kevin Cameron wrote:

>Arturo Salz wrote:
>
> > Attached is a new proposal for event (and the differences with the last 
> draft).
> >
> >     Arturo
>
>Definitely better :-)
>
>However I notice we're still not differentiating events and event 
>references - sec 12.8.
>I would prefer to drop 12.8 and just use references to events for the 
>extra functionality
>e.g.:
>         event ref ER = null;
>         event E;
>         ....
>         -> ER; // NOP
>         ....
>         ER = E;
>         ...
>         -> ER; // same  -> E
>
>- more or less the same functionality but I think it would be clearer to 
>users.
>
>Regards,
>Kev.
>
>
>--
>National Semiconductor, Tel: (408) 721 3251
>2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090