Data declared in an
automatic task, function or block has the lifetime of the call or activation
and a local scope. This is roughly equivalent to a C automatic variable. Data declared in a dynamic
process is also automatic.
The bit overlay rules
are the same as those for a packed union with the same member types: each
member shall be the same size, and connectivity is independent of the
simulation host. The types of nets connected with an alias
statement must be type compatible, that is, all the nets
they have to be of the same net-type. or “wire”; i.e. it would be
For example, it is illegal to connect a wand
net to a wor
net with an alias
statement. This is a stricter rule
than applied to nets joining at ports because the scope of an alias is limited
and such connections are more likely to be a design error. Variables and
hierarchical references cannot be used in alias statements. Any violation of these rules shall be
considered a fatal error.
Editor’s Note: I feel the preceding
paragraph is awkwardly and ambiguously worded.
Why is “wire” in quotes? Is this an
indication that it is not referring to the wire keyword? Even it that is the
intent, it is easy to assume that the specific keyword is intended, and
therefore that only the wire data type can be aliased. I suggest striking the
“or “wire” “, or replacing it with “or net”.
The same sentence says the alias
connection must be “compatible” and must be the “same type”. To me, those are
two different things. In Verilog, wire and tri are compatible, but are they the
same type?. In Verilog, wire and tri1 have
compatibility rules when connected together so there is no error or warning
(see section 12.3.10). Can they be aliased to each other?
What if I alias two nets, both wire types
of exactly the same size, but one is declared as signed (or is coerced to being
signed by being connected to a signed port in the containing module) and the
other wire is unsigned?
Editor’s Note: The statement that
implicit nets are assumed to be scalar is not accurate. For a module instance,
if an undeclared identifier is also declared as a port of the containing
module, then a net of the port size is assumed. I changed the wording as shown
above.