The balance of the sections
of this standard describes the behavior of each of the elements of the
language. This section gives an overview of the interactions between these
elements, especially with respect to the scheduling and execution of events.
Although SystemVerilog is used for more than not limited to simulation,
the semantics of the language are defined for event directed simulation, and everything else is other uses of the hardware description
language are abstracted from this base definition.
The sampling time of
sampled data for property expressions is controlled in the clock domain block.
The new #1step sampling
delay has
been added to provides the ability to sample data immediately before
entering the current time slot, and is a preferred construct over other
equivalent constructs
in order to because it allows the 1step time delay to be parameterized. This #1step
construct is a conceptual device mechanism that provides a method of for defining when sampling
takes place, and it is not creating a requirement does not require that
an event be created in this previous time slot. Conceptually this #1step
sampling is identical to taking the
data samples in the preponed region of the current
time slot.