library realLib *.svr; library logicLib *.sv; config cfgReal; design logicLib.top default liblist realLib logicLib; endconfig config cfgLogic design logicLib.top default liblist logicLib realLib; endconfig module top(); interconnect [0:3] [0:1] aBus; interconnect [0:3] dBus; driverArray driver[0:3](aBus); ctlBlock ctl(clk,rst); cmpArray cmp[0:3](aBus,rst,dBus); endmodule: top package NetsPkg; nettype real realNet; endpackage: NetsPkg `timescale 1ns/1ps module driver import NetsPkg::*; #(parameter delay = 30, iterations = 256) (output realNet [0:1] outD); assign outD = outR; initial begin outR[0] = 0.0; outR[1] = 3.3; for (int i = 0; i < iterations; i++) #delay outR[0] += 0.2; outR[1] -= 0.2; end endmodule: driver `timescale 1ns/1ps module driver #(parameter delay = 30, iterations = 256) (output logic [0:1] outD); initial begin outD = '0; for (int i = 0; i < iterations; i++) #delay outD++; end endmodule: driver `timescale 1ns/1ps module cmp import NetsPkg::*; #(parameter vsup = 3.3, slew = 0.005, hyst = 0.65) (input realNet [0:1] inA, input logic rst, output realNet outD); real updatePeriod = 100; real outR = 1.7; real rate = 0; assign outD = outR; always #updatePeriod begin if(outR + rate * updatePeriod > vsup) outR = vsup; else if(outR + rate * updatePeriod < 0.0) outR = 0.0; else outR += rate * updatePeriod; end always @(inA, rst) begin if(rst) rate = -1 * slew; else if(inA[0] > inA[1]) rate = slew; else if(inA[0] < inA[1] - hyst) rate = -1 * slew; end endmodule: cmp `timescale 1ns/1ps module cmp #(parameter vsup = 3.3, slew = 0.005, hyst = 0.65) (input logic [0:1] inA, input logic rst, output logic outD); real delay = vsup/slew; always @(inA, rst) begin if(rst) outD <= #delay 1'b0; else if(inA[0] & ~inA[1]) outD <= #delay 1'b1; else outD <= #delay 1'b0; end endmodule: cmp