library realLib *.svr; library logicLib *.sv; config cfgReal; design logicLib.top default liblist realLib logicLib; endconfig config cfgLogic design logicLib.top default liblist logicLib realLib; endconfig module top(); interconnect [0:3] aBus; interconnect [0:3] [0:7] dBus; driverArray driver[0:3](aBus); ctlBlock ctl(clk,rst); adcArray adc[0:3](aBus,clk,rst,dBus); endmodule: top package NetsPkg; nettype real realNet; endpackage: NetsPkg `timescale 1ns/1ps module driver import NetsPkg::*; #(parameter delay = 30, iterations = 256) (output realNet outD); real outR = 0.0; assign outD = outR; initial for (int i = 0; i < iterations; i++) #delay outR += 0.2; endmodule: driver `timescale 1ns/1ps module driver #(parameter delay = 30, iterations = 256) (output logic outD); initial begin outD = '0; for (int i = 0; i < iterations; i++) #delay outD =~ outD; end endmodule: driver module adc import NetsPkg::*; (input realNet inA, input logic clk, input logic rst, output logic [0:7] outD); ... endmodule: adc module adc(input logic inA, input logic clk, input logic rst, output logic [0:7] outD); ... endmodule: adc