0. Executive Summary SV-DC intends to provide capabilities in SystemVerilog to support efficient modeling of analog/mixed-signal circuit components. These models are to be simulated by the event-driven simulation engine and should, therefore, exhibit simulation performance comparable to digital models and be suitable for system level simulation. The new modeling capabilities will be achieved by natural extensions to the existing SystemVerilog language; no analog solvers or netlist manipulations will be required. 1. Motivation and Use Cases [why] The primary use case motivating SV-DC's work is the need for high speed simulation of models of analog blocks. Existing analog/mixed-signal simulations are not sufficiently scalable to accommodate platform and system level models. The envisioned solution is to enable modeling of such blocks in the discrete domain, trading accuracy for speed. Faster discrete models will be interchangeable in a plug and play style with continuous or conservative models. Effective discrete domain real modeling will require natural extensions to SystemVerilog, such as real-valued nets and ports, aggregate nets and ports involving real values, resolution functions, generic interconnects, and type conversion mechanisms. These modeling capabilities will support uses such as: -Design exploration and verification of larger integrated models. -Representing the inter-connect of an entire system. -Modeling mixed use signals. For example, the same wire may be driven at some times by a digital clock and at other times by an analog voltage. -Easy swapping of models with differing levels of abstraction but compatible interfaces. 2. Requirements [what] A. Net Capabilities Scalar Real Valued Net R01. [MUST] Real valued nets with multiple drivers R02. [MUST] Resolution functions for multiply driven real valued nets R03. [MUST] Ability to represent X (unknown) and Z (undriven/high impedance) states for real nets R04. [MUST] Unidirectional and bidirectional ports with real nets Aggregate Nets with Real Valued Components R05. [MUST] Aggregate nets with real valued components, including vectors, static arrays, structs, unions R06. [MUST] Resolution functions for multiply driven aggregate nets R07. [MUST] Bidirectional ports with aggregate nets R08. [MUST] Atomic aggregate nets whose components are resolved jointly (correlated resolution) R09. [MUST] Ability to represent X (unknown) and Z (undriven/high impedance) states for atomic aggregate nets B. Type Conversion and Compatibility R10. [SHOULD] Type conversion mechanisms to enable connection of nets of different, yet compatible, types and structures, including connection of aggregate nets R11. [SHOULD] Ensure design intent is clear when converting from logic to real valued domains, including voltage intent for signals C. Utilities for Real Modeling R12. [MUST] Generic interconnect constructs for structural connectivity R13. [MUST] Type coercion between generic interconnect and explicit types R14. [MUST] Capability to create aggregates of generic interconnect where individual selects or slices may connect to ports of different types R15. [MUST] Definitions of math functions and relational operators for real types in the presence of unknown and high impedence states R16. [COULD] VCD support for newly introduced nets R17. [COULD] Debug enhancements such as force/release/deposit, VPI, etc. for newly introduced nets, including OOMR read and write net access from testbench R18. [COULD] Delay on newly introduced nets D. Items for future PARs R19. [COULD] Enhanced real-valued net state with quasi-continuous signal functions, time constants, next-time points for reevaluation, etc. R20. [COULD] $tablemodel support with real net type R21. [COULD] Specification of dense time characteristics (e.g., slewed delay transition of a net, piecewise linear representation of the value of a net) R22. [COULD] Ability to specify power supply/domain on a real value net 3. Relationship to Verilog-AMS Verilog-AMS is part of the Verilog family of languages and has been standardized By Accellera. It is the Accellera plan that Verilog-AMS merges with SystemVerilog at some point in the future so that there is unified standard covering all the Verilog languages. SV-DC is aware that the proposed discrete domain real modeling capabilities will have some level of overlap with the capabilities provided by Verilog-AMS wreal. SV-DC is also aware that work to merge SystemVerilog and Verilog-AMS has started, although completion of the merger is expected to take at least three years. SV-DC itself intends neither to merge wreal into SystemVerilog nor to complicate this merger. Therefore SV-DC will study the mapping of Verilog-AMS wreal capabilities into the new real modeling framework. The expectation of SV-DC is that the overlapping functionality of Verilog-AMS wreal will map reasonably into the new SystemVerilog real modeling framework. SV-DC will communicate the results of this study to the Verilog-AMS Committee as an aid to merger activities. SV-DC will also take account of this study and feedback on it before finalizing 2A. 4. Timeline and Vision [when] SV-DC intends to address requirements marked with MUST and SHOULD priority in the timeframe of the 2012 PAR. Requirements marked with COULD priority will be addressed in the 2012 PAR as time permits or in future PARs.