[sv-dc] Preparing for the next PAR (work items)

Hi all,

As I stated in the previous e-mail the SystemVerilog/Verilog-AMS committee work has generated some thoughts about tasks for SV-DC.  I would like to use those ideas to seed the discussion about work items for the next PAR with SV-DC.  The list follows.  Please reply with additional commentary on the existing items or new items that should be on the list for consideration.  We will discuss and decide upon each item during the three planning meetings that will be scheduled soon.

1. Variable connections to user-defined nettypes (UDNs)
   a. Rules for interconnect abstraction resolution in the presence of variable connections
2. Switch primitives that support UDNs
3. Heterogeneous concatenations involving UDNs
4. Packed/unpacked port connections involving UDNs
5. Partial drive of UDN struct fields
6. Adapters (i.e., conversion elements) between non-matching UDNs
  a. Rules for selecting and specializing adapters
  b. Scheduling of adapter evaluation in the digital simulation cycle

It should be noted that item 6 is under discussion in the SV/VAMS committee.  The hope/expectation is that the SV/VAMS committee will develop a general proposal supporting mixed-signal adapters.  SV-DC can extract the digital-only portion of that work and use it more or less untouched.

Thanks,
Scott

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