[sv-dc] Result of Champion's vote on 3724

Hi all:

The Champion's completed a vote on 3724. The results are below:

Opposed:
Brad
   Before approving, I'd like to hear the official position of SV-DC about
   whether this is a divergence away from Verilog-AMS, and if so, why that
   divergence is considered necessary.

Friendly Amendments:
Stu
   Quotation marks are used in several places in the text where they should
   not be used (no person or document is being quoted). These quote marks can
   be removed by the editor when the proposal is added to the LRM.

I don't believe we need to change the proposal. I am suggesting a response to Brad as follows (I would like to thank Dave Miller for some of the text and ideas as I stole them directly from our e-mail conversation earlier today). Please let me know if you have any feedback on the response. A quick turnaround is desirable, so I will send the response to Brad about 48 hours from the time I send this message unless I get an objection.

The content of 3724 is not considered a divergence from Verilog-AMS. Although undocumented and undefined, many Verilog-AMS implementations use wire to carry electrical or wreal signals through the hierarchy. This will not work well in SV and is an issue the SV-VAMS merger committee would have been forced to address prior to the merger. The interconnect construct should be usable by both languages and is more of a convergence than a divergence for the SV-VAMS merger effort.

We would also like to mention that Ian Wilson is the designated Accellera representative to the SV-DC committee. His primary responsibility is to represent the interests of the Accellera Verilog-AMS committee within SV-DC. Ian has discussed both of the SV-DC proposals with the Verilog-AMS committee prior to the votes in SV-DC.

Thanks,
Scott

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