[sv-dc] Notes from meeting on 2011-09-21

2011-09-21
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SV-DC Meeting Notes

Attendees:
n -------------111111--11111 Jim Lear (Cirrus)
n --------------11111-11-111 Achim Bauer (EXL-Modeling)
n -----------------111111111 John Havlicek (Freescale)
v 11111111111111111111111111 Scott Little (Chair, Freescale)
v -1111111111-111-------1111 Scott Cranston (Cadence)
v -11-1--11111-1-11-1111111- Sundaram Sangameswaran (TI)
v -11111111-1111-11111111-11 Gord Vreugdenhil (Mentor)
n -----------1------1111-11- Top Lertpanyavit (Intel)
n -------------------------1 Dana Fisman (Synopsys)
n -1--1-11-1-11--1-11--1-1-1 Ghassan Khoory (Synopsys)
v 1111-1111----111-11111-1-- Ian Wilson (Accellera/BDA)
n -------------------------- Ken Bakalar (Mentor)
n -------------11--1111-111- Kevin Cameron (obs)
v 111-11-11111-111111-11-111 Arturo Salz (Synopsys)
v 111--11111-11-1--1-------- Dave Cronauer (Synopsys)
n -------------------------- Ed Cerny (Synopsys)
n ---------------------1--11 Tapan Halder (Synopsys)
n ------1111-111------------ Jonathan David (Qualcomm)
n -------------------------- Jim Holmes (Lynguent)
n -------------------------- Walter Hartong (Cadence)
v 11111111111111111111-11111 Shekar Chetput (Cadence)
n ----------------11111111-- Martin O'Leary (Cadence)
v 1111111111111111-----1---- Francoise Martinolle (Cadence)
n -----------------1--1----- Prabal Bhattacharya (Cadence)
v 11111111111-1111.......... Abhi Kolpekwar (Co-chair, Cadence)
v 11111111111111-1.......... Steven Sharp (Cadence)
n --1-11-11-1--1............ Kishore Karnane (Cadence)
n -----11-1----1............ Dave Miller (Freescale)
n ------1-11111............. Jess Chen (Qualcomm)
v 11111111111............... Mark Hartoog (Synopsys)
n --1....................... Shalom Bresticker (Intel)
  |-> attendance on 2011-09-21
|---> voting eligibility on 2011-09-21

Upcoming dates to note:
2011-10-01 - P1800 TC work ends

AK: We have completed our internal review of 3724. We have some concerns about whether the proposal allows nets of different types to be connected to the same interconnect.

SL: I think that Gord's recent e-mail has clarified that this is disallowed. If the interconnect net is resolved to one of the types it would be illegal to connect to the other type based on the collapsing rules in 3398.

SS: I understand that we were aren't allowing concatenation between interconnect and non-interconnect, but can you connect non-homogeneous items to a single interconnect? I don't see anything against that. It seems that the proposal allows heterogeneous interconnect arrays.

SL: Yes, I agree. It would be nice to add an example to help people understand that this behavior is allowed by the rules.

SS: I don't believe that the proposal is perfectly clear about whether you can concatenate interconnect arrays in a port expression. If it is allowed the concatenation would need to happen prior to the determination of the data types for the individual interconnect array bits. I would like to clarify this point. How about something like, "A concatenation of interconnects shall be considered a valid port expression even if different operands in the concatenation are resolved to different net types or data types." We could also generalize this statement to explicitly state that non-homogeneous interconnect arrays are legal. That would likely be sufficient.

SL: Okay, I will send a couple of suggestions along those lines to Gord to get his opinion. I will also add an example. After getting feedback from Gord, I will post an updated version of the proposal. My hope is that this can happen quickly, and I will call for an e-mail vote on this proposal that will finish prior to the Oct. 1 deadline.

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