RE: [sv-dc] 3398 proposal

From: Arturo Salz <Arturo.Salz@synopsys.com>
Date: Thu May 19 2011 - 12:45:12 PDT

Dave,

The restriction exists to prevent multiple, piecewise assignments to the net's components in order to provide a completely specified (atomic) value from each driver to the resolution function. Using your example, users might be tempted to do:

   assign mynet.val1 = value;
   assign mynet.abstol = tolerance;

   ...
   Value = 3.3;
   tolerance = 0.001;

The above code could have undesirable effects.

The LRM instead requires:
   assign mynet = '{value, tolerance};
OR
   T nv;
    assign mynet = nv;

Incidentally, there is a minor error in your example, a missing apostrophe in the assignment pattern => '{3.3, 1e-6};

        Arturo

-----Original Message-----
From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Dave Miller
Sent: Thursday, May 19, 2011 7:07 AM
To: sv-dc@eda.org
Subject: Re: [sv-dc] 3398 proposal

I have a question regarding 10.3.2.
Why the restriction on assignment? If I understand the paragraph correctly, you must assign to all of the user defined net. Since everything always has at least a default type why is this needed?

I was thinking something like this:
   typedef struct {
     real val1;
     real abstol=1e-6;
   } T;

   nettype T wT;

   wT mynet;

Does this mean if I want to drive a value onto mynet, I have to do:
   assign mynet = {3.3, 1e-6};
instead of just:
   assign mynet.val1 = 3.3;

I don't want to delay the proposal at all, and it is just a restriction that can always be relaxed at a later date once more use cases become available. But the more I thought about it, the more I failed to understand why have the restriction at all.

Of course I come from analog, so maybe the lack of state history and retention of values comes into play here which may be what I am missing? Excuse my ignorance with the SystemVerilog flow, still learning.

Regards
Dave

On 05/18/2011 09:38 AM, Gordon Vreugdenhil wrote:
> I have a few minor comments; if those could be updated prior to the
> meeting, I'd be fine with voting on the proposal today.
>
> 1) Shade of blue needs to be made consistent
>
> 2) In 6.6.7, just after the grammar:
> "A net declared with that nettype therefore uses ..."
> should say:
> "A net declared with a nettype therefore uses
>
> Similarly, in 6.7.1, second sentence:
> "A net declared with that nettype uses the ..."
> should say
> "A net declared with a nettype uses the ..."
>
> 3) In the 6.6.7 and 6.22.6 examples, there is the following:
> // if nettypeid1 is a nettype, create another nettype name nettypeid2
> Why is this a conditional statement? It should be something like:
> // declare another name nettypeid2 for nettype nettypeid1
>
> 4) In 28.12, there is a missing period at the end of the blue text.
>
> 5) The "open items" must be removed from the proposal.
>
> Gord.
>
>
> On 5/13/2011 2:08 PM, Francoise Martinolle wrote:
>> Hi Scott,
>> I forgot to mention that this proposal version 7 can serve as the
>> basis of the vote for Wednesday.
>> Francoise
>> '
>>
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> --------------------------------------------------------------------
> Gordon Vreugdenhil 503-685-0808
> Model Technology (Mentor Graphics)gordonv@model.com
>
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Received on Thu May 19 12:45:49 2011

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