[sv-dc] 3-D vs Enums

Another note on 3-D.

The original concept of 3-D is based on a 2-D version that Craig Amey introduced me to at MetaSoftware, i.e. in low-level logic you can separate the calculation of the logic value from the calculation of it being unknown. This means that you can accelerate the simulation of logic circuits by computing the two components in parallel - important if you build h/w simulation accelerators, or just want to do them as separate event-driven calculations. If you use an enum instead (as is usual in VHDL) you have to do extra work to separate the value (1/0) from the certainty/strength (X/Z) when computing logic.

Using 3-D representations is beneficial in mixed-signal because handling 'X'/'Z' values is very awkward, if you have both the 'X'/'Z' data and a value, you can use the value to compute a valid circuit state even if you are not 100% confident, i.e. if you are initializing logic with a 3-D model the signal values will be consistent regardless of the certainty, so if you have to convert any signals into analog (or Thevenin/wreal), then the analog should be able to find a matching state for the logic and the entire circuit will be in a valid state.

The designer intent is also clearer with 3-D than it is with enums, which makes life easier for synthesis tools.

Kev.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.