[sv-dc] conclusion

Hi,

I just had a talk with Jim and it turned out, that everything should be
doable with the methodology we discussed in our last meeting.
In my opinion we have arrived at a very strong methodology now and I did
not realize that in our last meeting, because frankly a few months ago I
did not expect that we can agree on something like this.

So all we need is:

1) an interconnect MODULE (like depicted in Jim's early mail) with a
full-fledged module body, that e.g. allows to schedule signals or events
ot to instantiate a capacitor or to specify a concurrent f(t) function

2) a powerful port type (aggregate or struct...) that passes (dynamic)
attributes and e.g. supports a Thevenin/Norton-style
(pseudo-conservative) modeling

With 1) and 2) we can do e.g. extremely fast (explicit) resolution of
multi-driven real-value nets, or somewhat slower "analog-flavoured"
things like board-level simulation, backannotation of parasitic networks
or dealing with lumped Rs and Cs in a "real-value" netlist.

I.m.o. this means we are practice-proof :)

Thanks,
       Achim

P.S.:
to make all this perfect we might still have to talk a bit about a
(bidirectional) synchronization scheme, but maybe this is really
something for the next step.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.