[sv-dc] Modular compile etc.

I think Arturo registered some worries about optimizing/modular
compilation with a more generalized type scheme. I think it's worth
pointing out that there are a number of things that already get in the
way of doing that:

   1. Parameters
   2. Cross module references
   3. Defparams
   4. Back annotation
   5. Driver strength (inc. debug forcing)
   6. Inability to identify need for resolution prior to elaboration

Adding the general cross-type resolution scheme I'm thinking of is on a
par with the last two items. At the code-generation level all it does is
separate the driven data from the received data for a given wire in a
given module, the types of the module's drivers and receivers do not
change - which is the general case as SV stands. New types can be
treated much the same as an extended strength value, and can be handled
outside of the module code.

I think there was also some confusion between the semantic model, and
the resulting behavior. Changing the semantic model does not
necessarily change the behavior, i.e. considering interconnect as
untyped and only drivers and receivers as typed should give exactly the
same behavior for existing Verilog as before.

Kev.

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