Re: [sv-dc] SV-DC meeting reminder (2010-11-17)

For some related functionality to that in the Thevenin modeling, you
might want to look at section 9.21 on "driver access" in the AMS LRM -

http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.3.1/VAMS-LRM-2-3-1.pdf

- which is aimed at helping convert digital signals into analog.

I think the idea was that a function like -

  $driver_state ( signal_name , driver_index )

- would be implementable as a PLI call in Verilog, but I think going
forward (in SV) something like:

  signal_name->driver(driver_index)->state()

would make more sense.

Rick Munden and I tried to get some of this AMS support into VHDL using
implicit signals, but the proposal failed to get to a vote. It would
have been something like -

  signal_name'driver(driver_index)'state

I think there was originally another function like
"$my_driver(signal_name)" which could be used to get the index of a
process's own driver, but it isn't useful in a connect-module context.

Kev.

On 11/16/2010 03:28 PM, Little Scott-B11206 wrote:
> Hi all:
>
> This is a reminder that SV-DC will meet on 2010-11-17 from 11:00 - 13:00
> (UTC-06:00). Note the time adjustment. In the US we have changed to
> winter time. The agenda and dialin information are below.
>
> Agenda:
>
> 0. IEEE patent policy
> See: http://standards.ieee.org/board/pat/pat-slideset.ppt
> 1. Thevenin modeling example discussion by Jim Lear (example is
> attached)
>
> Thanks,
> Scott
>
...

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