[sv-dc] questions on todays presentation

Hi Shekar,

thanks for today's presentation ! Unfortunately there was not enough time left for questions,
so I send you two questions on electrical-to-real issues, that I would be interested to know more about.

1)
If you sample e.g. an electrical, periodic rail-to-rail signal "periodic_signal" with
always @(absdelta(V(periodic_signal),VDD/100)) rendered_real = V(periodic_signal);
This might produce a minimum of 200 additional time points per period (if I do not misunderstand it).
Depending on the time step relaxation algorithm this might even result in over thousand additional time steps !
Since typically "rendered_real" will be read event-based somewhere for further processing anyway,
why not somehow trigger the analog side, so that "rendered_real" is just updated "on demand" and once,
i.e. at the event when (or eventually at the threshold where) it is read ?

2)
Imagine you are having two drivers, that drive a common net (that may subsequently be read by some real-value model).
One of the drivers shall be electrical, e.g. an ideal voltage source of 10V with a 8KOhm resistor in series;
the other driver shall be wreal with the value 1(V) and shall have an associated driving strength of 1KOhm.
So the correct result for the common net would be 2V.
How does your flow/methodology produce this result (when connect modules are used) ?

Thanks,
           Achim

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