Re: [sv-dc] SV-DC roadmap update

Hi All.

I would like to see Verilog-A/MS standardized by IEEE, but
I would not want it absorbed into the current 1800 work.

Rather, perhaps, Verilog-A/MS might be
specified, eventually, in "1800.1" or some such
independent document.

Right now, "Verilog" is somewhat ambiguous, because
it has no active Std (of course, 1364-2005 still is available).
Students (and I) are reluctant to spend about $300 for a
Verilog Std document most of which they will not use, in part
because tool support is so spotty.

As a teacher of Verilog-A/MS, I'd like to have a document
which unambiguously specifies it. Right now,
Accellera provides this; but, if IEEE adopts it as a
mere chapter of 1800, it will become much harder to expect
students to use it as a reference.

So, I agree that DC should take into consideration the current
status of Verilog-A/MS but should follow its own path.

On 09/15/2010 07:06 AM, Gordon Vreugdenhil wrote:
>
>
> On 9/15/2010 12:01 AM, Martin O'Leary wrote:
>>
>> I agree that SV-DC shouldn't be integrating SV and AMS standards.
>> However, it does not serve the Mixed Signal users or the SV-AMS merger
>> if SV-DC goes off in completely different directions and doesn't
>> take account of Verilog-AMS.
>
> I don't think that anyone is suggesting that we ignore V-AMS. I've
> certainly never heard anyone say or insinuate that we should do
> so.
>
> There are a couple of issues with formally committing to do anything
> cross-language:
> 1) The IEEE does not own or control the V-AMS spec, nor does
> the 1800 committee. There are real issues in having the
> standard say anything normative outside its bounds.
> 2) As Arturo noted as well, committing to defining mappings
> (assumably bi-directional) can overly constrain committees.
> 3) Any commitment on this front would likely open up concerns
> and levels of discussion that are more appropriate when and
> if SV and V-AMS formally merge into some standard.
>
> I think the wording we have strikes a good balance -- it clearly
> acknowledges that the DC work does not exist in a vacuum and
> clearly indicates that DC will consider V-AMS constructs in terms
> of their relationship to SV-DC proposals *in order* to not
> complicate any potential merge of the standards.
>
> So, no, we're not committing to *do* the work involved with
> a merge (or direct mapping of constructs), but we're definitely
> committing to spending effort to understand alignment issues
> and make intentional decisions about where the discrete modeling
> functionality should go.
>
> Gord.
>
>> I would like to get a better understanding of your specific concerns
>> at the call tomorrow.
>>
>> I am hopeful we can work out the wording needed to address all of
>> our important concerns.
>>
>> Thanks,
>> --Martin
>>
>>
>>
>> Martin O'Leary | AMS Designer Team | Cadence
>> P: (408) 428 5206 www.cadence.com
>>
>>
>> -----Original Message-----
>> From: Arturo Salz [mailto:Arturo.Salz@synopsys.com]
>> Sent: Tuesday, September 14, 2010 4:17 PM
>> To: Gordon Vreugdenhil; Martin O'Leary
>> Cc: Achim Bauer; Ian Wilson; Little Scott-B11206; sv-dc@eda.org
>> Subject: RE: [sv-dc] SV-DC roadmap update
>>
>> I share some of Gord's concerns. I believe the current roadmap text is
>> good enough and needs no additional commitments that might
>> over-constraint SV-DC and impede accomplishing its primary goals. It
>> is not the charter of SV-DC to integrate the SV and AMS standards -
>> that integration is a considerable effort that will happen in due time.
>>
>> Arturo
>>
>> -----Original Message-----
>> From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of
>> Gordon Vreugdenhil
>> Sent: Tuesday, September 14, 2010 2:09 PM
>> To: Martin O'Leary
>> Cc: Achim Bauer; Ian Wilson; Little Scott-B11206; sv-dc@eda.org
>> Subject: Re: [sv-dc] SV-DC roadmap update
>>
>>
>> Martin,
>>
>> I think that SV-DC should focus on its mandate -- how
>> to introduce mechanisms for discrete modeling into SV.
>> It is not part of our mandate to begin any AMS integration
>> nor to define a definite mapping to AMS features. Given
>> that there would likely be an expectation that such a
>> mapping would be invertible, I'd likely oppose any commitment
>> to such a mapping as there are aspects of current AMS
>> definitions with which I seriously disagree.
>>
>> I think the current text in the roadmap strikes a reasonable
>> balance -- it says that DC will be aware of and will
>> consider AMS alignment points and future potential
>> directions without any commitment or a priori constraints
>> on solutions that while not exactly the same as AMS,
>> may be more appropriate in a digital context.
>>
>> Gord.
>>
>> On 9/14/2010 1:53 PM, Martin O'Leary wrote:
>>> I totally agree that better coordination with SV-DC and SV-AMS is
>>> needed.
>>>
>>> I think this is very important as they are both planning to do a lot
>>> of work in the next year or so and could easily trip over and
>>> undermine each.
>>>
>>> However I think the coordination mechanism needs to better defined
>>> and have clearer goals and responsbilities.
>>>
>>> Along the same line, section 3 of the roadmap (relationship to
>>> VerilogAMS) has a lot of words but doesn't seem to commit anything
>>> really. It seems
>>>
>>> pretty wishy, washy. One thing that would be helpful in this regard
>>> would be commitment to define the mapping rather than just study it.
>>>
>>> Without some clearer commitments including coordination mechanisms, I
>>> am very concerned that the committees won't coordinate very
>>>
>>> well, despite a significant amount of shared members.
>>>
>>> Thanks,
>>>
>>> --Martin
>>>
>>> *Martin O'Leary* | AMS Designer Team | Cadence
>>> P: (408) 428 5206 www.cadence.com<http://www.cadence.com>
>>>
>>> --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
>>>
>>>
>>> *From:* owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] *On Behalf
>>> Of *Achim Bauer
>>> *Sent:* Tuesday, September 14, 2010 1:34 PM
>>> *To:* Ian Wilson; Little Scott-B11206
>>> *Cc:* sv-dc@eda.org
>>> *Subject:* Re: [sv-dc] SV-DC roadmap update
>>>
>>> Hi Ian, hi Scott,
>>>
>>> I think it is a great idea to have regular meetings for discussing
>>> issues of interest.
>>>
>>> A specific goal might be e.g. to develop a methodology for
>>> CM-insertion/resolution/synchronization
>>>
>>> of mixed nets that transport electrical, real/aggregate and digital
>>> data.
>>>
>>> Another (longterm-)issue might be to brainstorm about a clean
>>> integration of ASVA within analog Verilog-AMS blocks.
>>>
>>> Best regards,
>>>
>>> Achim
>>>
>>> ----- Original Message -----
>>>
>>> *From:* Ian Wilson<mailto:ian.wilson@berkeley-da.com>
>>>
>>> *To:* Little Scott-B11206<mailto:B11206@freescale.com>
>>>
>>> *Cc:* sv-dc@eda.org<mailto:sv-dc@eda.org>
>>>
>>> *Sent:* Tuesday, September 14, 2010 10:06 PM
>>>
>>> *Subject:* Re: [sv-dc] SV-DC roadmap update
>>>
>>> I agree that it would be a good idea to have a regular sync-up meeting.
>>> Can we come up with a specific goal rather than to discuss issues of
>>> interest?
>>>
>>> --ian
>>>
>>> ----------------------------------
>>>
>>> Ian M Wilson
>>>
>>> Architect
>>>
>>> Berkeley Design Automation
>>>
>>> Office: 408-496-6600 x238
>>>
>>> Cell: 714-272-7040
>>>
>>> ian.wilson@berkeley-da.com<mailto:ian.wilson@berkeley-da.com>
>>>
>>> http://www.berkeley-da.com
>>>
>>> ----------------------------------
>>>
>>> True SPICE accuracy, 5X-20X faster
>>>
>>> Don't Be Left Behind!
>>>
>>> ----------------------------------
>>>
>>>
>>>
>>>
>>>
>>> Little Scott-B11206 wrote:
>>>
>>> Hi all:
>>>
>>>
>>>
>>> After attending the recent Verilog-AMS and SV-DC meetings and thinking
>>>
>>> about the happenings there it seems to me that it would be nice to have
>>>
>>> a regularly scheduled sync-up meeting to ensure that both groups are
>>>
>>> aware of each other's progress and technical issues of common interest.
>>>
>>> As such, I think we should add the following statement to the
>>>
>>> "Relationship to Verilog-AMS" section of the roadmap. Thoughts?
>>>
>>>
>>>
>>> Subgroups of the Verilog-AMS and SV-DC committees will meet regularly to
>>>
>>> discuss technical issues of interest between the two committees.
>>>
>>>
>>>
>>> Thanks,
>>>
>>> Scott
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
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>>
>

-- 
      John Michael Williams
      Senior Adjunct Faculty
Silicon Valley Technical Institute
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