Hi Achim.
Verilog-A/MS allows automatic insertion of connectmodules,
by declaring connectrules blocks. So it is possible to
avoid explicit instantiation of them under many conditions.
The problem would become significant for designs
which included instances wired to different
supply voltage levels, I think. Level-shifters, etc.
If a connectrules (or similar) block could be declared
inside of a module, most of the problem would be solved
without new resolution protocols.
On 08/18/2010 01:43 PM, Achim Bauer wrote:
...
>
> My opinion about whether connect modules are required for a purely discrete
> simulation is also not solid.
> I just have a gut feeling, that they might be indispensable, if we specify a
> weak resolution methodology
> and that they become unnecessary, if we go for a strong methodology.
--
John Michael Williams
Senior Adjunct Faculty
Silicon Valley Technical Institute
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