RE: [sv-dc] SVDC roadmap contribution

Hi Achim:

I just had a few questions based on a quick read.

* resolve a net with mixed real and digital adjacent ports
        à avoid connect modules and hiding/loosing information for a clean resolution

What do you mean by adjacent ports? When you say avoid connect modules, why is this necessary? Is this because connect modules hide or lose information? Can you elaborate?

* assert compatibility of power/supply domains around a rv-net
        à e.g. to verify missing/inappropriate level shifters

Is this something that can be checked statically at say elaboration time or is there a need to check this dynamically? I guess my question gets at could this be dealt with by the elaborator detecting that nets of two different domains are connected w/out a level shifter or are you envisioning more complex checks?

four-state (w)-real

full implementation of the wreal-donation

What do you mean by this? Are you talking about the wreal donation from Cadence to the Verilog-AMS committee or something else?

Thanks,

Scott

From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Achim Bauer
Sent: Wednesday, August 18, 2010 9:18 AM
To: sv-dc@eda.org
Subject: [sv-dc] SVDC roadmap contribution

Hi,

attached I send you my two-page contribution.

I shortly listed a few application cases and related implementation requirements.

Hope, it blends well with what we already have.

Thanks,

            Achim

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