[sv-dc] Power related proposals

http://www.verilog.org/mantis/view.php?id=1754 < specifying power
connections
http://www.verilog.org/mantis/view.php?id=2343 < AMS fix

SDF is pretty useless in this area, so here's an alternative -

http://www.eda-twiki.org/cgi-bin/view.cgi/VerilogAMS/BackAnnotationProposal

- works for ECOs too.

Note: this stuff is mostly about elaboration/connectivity and not
run-time behavior.

Kev.

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