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Subject: [sv-dc] Type confusion
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IMO the Verilog-LRM(s) don't really reflect what is/has a type properly.
A number of things in Verilog are implicit and are confusing to casual
users.
A typical case is that of "wire" and "reg", which really declare
semantic objects rather being type declarations - the type being
implicit. What the "wire" declaration does is create in the local scope
a connection point for drivers and receivers which maps to a physical
wire in the design (Verilog originally being a gate level simulator).
The "reg" declaration does the same thing but adds a local driver with
the (default) type "logic" which can be used in behavioral code. So
when you say -
reg foo;
always @(reset) foo = 0;
always @(clock) foo = !foo;
- a wire is created for "foo", a driver of type "logic" for it, and the
assignments to foo actually goes through the driver. Connections through
ports to other modules only deal with the "wire" part of foo. Signal
resolution looks at all the drivers attached to the wire.
Since you can determine from usage that "foo" needs a driver, the reg is
somewhat redundant, it was probably only there to make parsing easier in
the original tools. So SV allows the use of "logic" instead of "reg",
but that creates some ambiguity since what you end up with depends on
usage (instead of just the declaration).
For me the logical extension of the language is to say that you can use
explicit types with the existing declarations, i.e.
wire w;
reg x;
Can be replaced with (and is equivalent to) -
wire logic w;
reg logic x;
For a real-valued net -
wire real w;
reg real x;
- the underlying wire has no type, but in the local context and drivers
attached to will have type real. If you want a resolved type you then do
something like:
class res_real : extends Signal #(real); // Signal is a built-in
template
function real resolver(real values[]);
...
endfunction
endclass;
reg my_real x;
In this case the fact that my_real is built on the Signal template means
you can discard the "reg" and determine if you need a driver from usage.
A class based on the Signal template has "primitive" semantics (as in
Gord's proposal).
In a similar vein "assign w = 1" is the same as "assign logic w = 1",
and you can reuse the syntax with other types - e.g.:
assign real vdd = 1.5; // creates wire with single driver of
unresolved type "real"
assign real vss = 0.0;
Backward compatible, no new keywords.
Notes:
You might want to use the "reg" syntax to create a driver to be used
from DPI code when SV usage won't create one.
Net types like "wor" etc. are just a shorthand for saying create a wire
and the (locally) attached driver obeys wired-or resolution rules, i.e.
a "net type" is really a "resolution rule" for driver being declared.
Kev.
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