Re: [sv-dc] RE: Framework directions for discrete modeling

Please don't read too much into the keyword "primitive" in
what I wrote -- I just picked that as an existing keyword
that could unambiguously describe the syntax. There is
substantial resistance to adding new keywords in SV so I
just picked something that had at least some suggestion
of intent (that this composite net behaves atomically like
a primitive net in your terms).

Gord.

Kevin Cameron wrote:
> I'm just saying the resolution mechanisms in VHDL which tie in with the
> use of port-bound type conversions are the wrong thing to do if you want
> your AMS stuff to work.
>
> Having said that, you can have it both ways by adding a keyword like
> "primitive" (as suggested by Gord) to indicate that a type is resolved
> flat rather than hierarchically. In which case if you see "primitive"
> drivers on a net you can't do hierarchical resolution - noting that the
> SV type "logic" is a "primitive" type, so you might want to do it the
> other way round and mark non-primitive types as (say) "abstract".
>
> You can look at this as "primitive" (net) types represent physical
> things (actual wires), "abstract" may represent physical things but
> don't have to.
>
> Currently all net types in Verilog are "primitive", all types in VHDL
> are "abstract".
>
> Kev.
>
> On 07/28/2010 08:00 AM, Lear, Jim wrote:
>> Kevin Cameron wrote:
>>
>>> Resolution in Verilog is flat, i.e. hierarchy is not considered. VHDL
>>> does not do flat resolution, and that can give incorrect behavior
>>> for AMS.
>>>
>> I don't see were this could be a problem for a properly formed
>> resolution function. Thevenin and Norton resolution functions are
>> fairly robust.
>>
>> Kindest Regards,
>> Jim Lear
>> Cirrus Logic
>>
>

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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