Re: Strawman Ideas for SV-DC

I would suggest that rather than try to define new types like "4-state
real", the existing types need to be migrated into user-space (as VHDL)
and support added for operator overloading, such that some other
committee or user group can work out what types they need and implement
them without having to consult the IEEE. This one in particular seems to
run smack into Cadence's proposal for wreal at the AMS committee and
looks inferior to the Mentor proposal from Ken.

http://www.vhdl.org/verilog-ams/hm/3032.html

http://www.vhdl.org/verilog-ams/hm/index.html << search for wreal

Kev.

On 07/14/2010 08:43 AM, Arturo Salz wrote:
>
> Attached are some preliminary ideas on how to achieve the short term
> objectives of the SV-DC committee. We would like to share these with
> the SV-DC committee.
>
>
>
> Arturo
>
>
>
>
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