Date: Thu Jul 15 2010 - 12:39:21 PDT
This email is intended to explain why a resolved scalar port value can
not be used to model many simple electrical systems.
Consider a simple example of a bandgap/current reference circuit. The
bandgap put out an accurate reference voltage and that reference voltage
was driven to an external precision resistor. The current drawn through
the resistor is mirrored in the bandgap and used as a precision
reference current for use within the chip.
Chip Netlist
The chip netlist, or at least the analog portion of it, is derived from
the schematics. The schematics are used to define the topology of the
circuitry, and by using the schematics to generate the netlist, we can
verify the interconnect is correct. This topology and partition is
generally dictated by layout and system design concerns, and it can not
be violated for modeling purposes. If this is violated, we are not
checking the interconnect appropriately.
Bandgap Module
This is an elemental block level model. At this level and below is pure
model, and above it is schematic interconnect. It generates the Vref
voltage, and it must detect the current flowing through the Vref port.
Because this circuit and model may be reused in many different products,
one cannot assume any knowledge of the external resistance.
Rref
Rref is a reference resistor. It has no inherent knowledge of any other
circuitry around it or attached to its ports. These resistors have
nominal values as well as tolerances. The simulations may require that
the values vary from minimum to maximum. Additionally, these components
can be temperature sensitive. So the value of Rref will change.
From the voltage across its ports it can easily calculate the current
flowing through it. Similarly, from a current through its ports it can
calculate the voltage across the ports. However, that information is
useless unless it can be transmitted to the devices to which it is
attached.
Sometimes these resistors are a part of the schematics. For example,
there are often ESD resistors (and diodes to, BTW) in the pads.
Vref
Vref is the port on the Bandgap Module, the Chip Netlist, and it is also
the net above the Chip Netlist. It attaches to one of the ports on the
resistor. Not only must the Vref net transmit the value of the Bandgap
driver voltage, but it also must transmit the current being sunk in the
resistor.
Solution 1
One common solution I've seen used in Modeling systems such as Simulink
is to create two ports for Vref: Vref_v and Vref_i; The Vref_v is an
output of the bandgap model and an input to the resistor. The resistor
puts out a Vref_i and it is input back to the bandgap.
This solution has some problems.
1. It is a one to one "port". For example, one can not attach an
arbitrary number of resistors in parallel to the Vref port.
2. It is not a really single port for Vref, but two ports. This is
not compatible with schematic netlisting.
3. There are two flavors of electrical "ports". One drives voltage
and inputs current. The other drives current and inputs voltage. They
are not interchangeable.
Solution 2
The Thevenin equivalent driver is described in
http://www.eetimes.com/design/automotive-design/4009407/Model-discrete-c
omponents-in-VHDL
This solution provides a uniform, bi-directional port and a relatively
straightforward resolution function. I've been able to use it to model
second order impedances with discrete R, L, and C, devices with few
problems. Higher order systems are more efficiently modeled in solvers.
Solution 3
The Thevenin resolution function is not the only solution. The
interface mechanism was also discussed, and I've seen implementations
that use the interface. An interface will conceivably allow one to
model the interconnect as a circuit in itself. This comes in handy when
there are parasitic capacitances, resistances, and aggressor nodes that
are derived from layout. State space techniques could probably be used
to produce accurate results of high order parasitics efficiently in a
logic simulator without the need for equations solvers.
However, this does not negate the need for a Thevenin type of port.
Also, when a device model drives a value onto a Thevenin net, it must be
able to read the "resolved" value of all the drivers in order to
determine, for example, how much current is being drawn.
Kindest Regards,
Jim Lear
Cirrus Logic
(512) 851-4612
(512) 293-7248 (mobile)
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