Re: AW: SV-DC meeting 2010-05-25

Perhaps; although that is perhaps assuming the end result.
If you don't like "approximate" how about "more abstract"?

Gord.

Achim Bauer wrote:
> Hi Gordon,
>
> since models naturally are approximate,
> I would suggest in stead of
> "...approximate models for analog blocks"
> to evtl. use
> "...real-valued functional or signalflow models for analog/mixed-signal
> blocks"
>
> Achim
>
>
> -----Ursprüngliche Nachricht-----
> Von: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] Im Auftrag von Gordon
> Vreugdenhil
> Gesendet: Dienstag, 25. Mai 2010 16:08
> An: Havlicek John-R8AAAU
> Cc: sv-dc@eda.org
> Betreff: Re: SV-DC meeting 2010-05-25
>
> I have two minor suggestions on the proposed scope document.
>
> I'd reword:
>
> It is expected that these features can exist in SystemVerilog
> without a SystemVerilog/Verilog-AMS merger.
>
> as
>
> It is expected that these features can exist in SystemVerilog
> without requiring a merge of the SystemVerilog and Verilog-AMS
> standards.
>
> And then for:
>
> The primary use case motivating this work is the need for
> high speed AMS models.
>
> I would say:
>
> The primary use case motivating this work is the need for
> high speed simulation of approximate models for analog blocks.
>
> "High speed AMS" has "analog mixed-signal" which may be a bit misleading in
> terms of intent.
>
> Gord.
> --
> --------------------------------------------------------------------
> Gordon Vreugdenhil 503-685-0808
> Model Technology (Mentor Graphics) gordonv@model.com
>
>

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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