Re: SV-DC meeting 2010-05-25

I have two minor suggestions on the proposed scope document.

I'd reword:

    It is expected that these features can exist in SystemVerilog
    without a SystemVerilog/Verilog-AMS merger.

as

    It is expected that these features can exist in SystemVerilog
    without requiring a merge of the SystemVerilog and Verilog-AMS
    standards.

And then for:

    The primary use case motivating this work is the need for
    high speed AMS models.

I would say:

    The primary use case motivating this work is the need for
    high speed simulation of approximate models for analog blocks.

"High speed AMS" has "analog mixed-signal" which may be a bit
misleading in terms of intent.

Gord.

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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