module test;

  reg [8*12:1] s, t;
  reg [8*24:1] r;
  initial
    begin
      s = "test";
      t = ".txt";
      r = {s,t};

      $display("display(), s:%s", s);
      $display("display(), t:%s", t);
      $display("display(), r:%s", r);

      $getstr1({s,t});       // Causes acc_fetch_tfarg_str( ) to assert.

      $getstr1(r);

      $getstr2({s,t});    // We assert on a vscOperation

      $getstr2(r);

      $getstr3({s,t});

      $getstr3(r);

      $getstr4({s,t});

      $getstr4(r);
    end

endmodule