module pipe2 (
  output logic q,
  input        d, clk, rst_n);
  logic        q1;
  logic        pu1 = 1'b1;

  wire rst2_n = pu1;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  q <= '0;
    else         q <= q1;

  always_ff @(posedge clk or negedge rst2_n)
    if (!rst2_n) q1 <= '0;
    else         q1 <= d;
endmodule


