module pipe1 (
  output logic q,
  input        d, clk, rst_n);
  logic        q1;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  q <= '0;
    else         q <= q1;

  always_ff @(posedge clk)
    q1 <= d;
endmodule


