interface abc_if(input wire clk, 
                  input wire reset_n);
  timeunit 1ns; timeprecision 100ps;
  wire  a, b, c;
  logic d;
  assign c=!a;
  modport fslave_if_mp (output c, d,
                       input  a, b);
  parameter hold_time=3;  // 3ns  
  parameter setup_time = 5;
endinterface : abc_if

module m(input logic clk, input reset_n, 
           abc_if.fslave_if_mp slave_if1);
  always @ (posedge clk) begin 
    ap_proc: assert property(@ (posedge clk) 
      $rose(slave_if1.a) |=> slave_if1.b);
    slave_if1.d <= slave_if1.c; 
  end 

  ap_conc: assert property(@ (posedge clk) 
      $rose(slave_if1.b) |=> slave_if1.c);

  logic a=1, b=0, c;
  ap_abc: assert property(@ (posedge clk) a|-> b |-> c);
  ap_bc: assert property(@ (posedge clk) b |-> c);
  


endmodule

module top; 
  logic clk=1'b1, reset_n;
  logic a=0, b=0;
  abc_if #(.setup_time(3), 
           .hold_time (3)) top_if(clk, reset_n);
   m m1(.clk(clk), .reset_n(reset_n), .slave_if1(top_if));
  initial forever #10 clk=!clk;
  always @ (posedge clk) begin
   ap_1: assert(randomize(a, b));	
  end
  assign top_if.a =a;
  assign top_if.b=b; 

endmodule : top