// interface 
interface test_if(input clk); 
 wire a, b, c;
 modport driver_if_mp (
         output c,
    	 input  a, b);
endinterface 


module test; 
  logic clk=1'b1, ex=0, aa=0, bb=0, cc=0; 
  test_if f_if (clk); 
  class test_class; 
    virtual test_if.driver_if_mp f_if;
    function new(virtual test_if.driver_if_mp  new_vir_if);
      this.f_if = new_vir_if;
    endfunction : new
  task run_c();
	ex <=0;
    expect ( @(posedge clk) f_if.a |-> ##2 !f_if.a);
	if(f_if.a) $display("f_if.a= %b", f_if.a);
	ex <= 1'b1;
  endtask 
  endclass 

  test_class tc = new(f_if); 
  initial forever #10 clk = ~clk; 
  always @ (posedge clk)  begin 
     tc.run_c;
  end

  always @ (posedge clk)
	assert(randomize (aa, bb, cc));

  assign f_if.a=aa;
  assign f_if.b=bb;
  assign f_if.c=cc;

  initial #300 $finish; 

endmodule