Minutes SV-AC 04/10/03
Written by: Stephen Meier

ATTN: Next SV-AC Meeting Th April 10th 9:30-10:30AM PST 
	Dial-In = 888-830-6260
	Intl: 1-505-242-2420
	PartID = 908704

Legend:
	x = attended
	- = missed
	r = represented
	. = not yet a member
	v = valid voter (3 out of last 4)
	n = not valid voter

v[xxxxxxxxxxxxxxxxxxx----x.] Faisal Haque (Cisco, Chairman)
v[xxxxxxxxxxxxxxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair)
v[xxxxxx-xxxxxxxxxxx-xxx--x] Roy Armoni (Intel)
v[xrxxxxxrxxxxxxx-x-xxxrxx.] Surrendra Dudani (Synopsys)
v[xxxxxxxxxxxxxxxxxxxxxrxrx] Cindy Eisner (IBM)
v[xxxxxxxxxxxxxxxxrxx-xxx..] John Havlicek (Motorola)
v[-xxx--xxrxxxxxx-xx-xxxxx.] Richard Ho (0-in)
v[xxxxxx-xxxx-xxxxxxxxxxrx-] Adam Krolnik (LSI)
v[xxxxxxxxxx-xxxxxxxxx---xx] Joseph Lu (Sun)
v[xxxrx--xxxxxxxxxxxx--xxxx] Erich Marschner (Cadence)
v[xxx-x-xxxrxxxx-x-xxxxxx-x] Andrew Seawright (0-in)
v[-xxxxxxxxxxxxxxxxx-xrxxxx] Bassam Tabbara (Novas)
v[xxxx-x-xxxxx.............] Tej Singh (Mentor)
n[-x--xx-xxxx..............] Connie O'dell (Consultant)
v[--xx-x-xxx-x--xxx-x--xx-x] David Lacey (HP, OVL Chairman)
v[---x-xxxxx---x...........] Hillel Miller (Motorola)
v[----xxxx.................] Kurt Shultz (Motorola)

n[----x--------------------] Ping Tseng (Axis)
n[-------xxxx-x-xxxxx-xxxx-] Prakash Narain (Real Intent)
n[---------xx-xxx-rx-xxxrrx] Harry Foster (Verplex)
n[----------xx-----xxxxxxx.] Ambar Sarkar (Paradigm Works)
n[------------xxxxx........] Yaron Wolfsthal (IBM)
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1. Review Issues from Prior Meeting Section 17.1-17.7

No issues

2. Review of Sections

17.9 - 
	Update to include SV3.0 system functions

	What is definition of $rose, $fell, $stable when the sampling
	clock does not occur or the previous clock did not occur? 
	Agreed to define past value as x, and value as posedge, negedge.

	Erich asked what happens if boolean expression evaluates to x, what
	is definition of sequence.  LRM needs to define boolean satisfaction
	relation.  Answer: x is cast to zero.

17.10 - Property definition

	Surrendra updated that variable declaration will be updated to not
	allow static variables.

	sequence declarations will be removed based on decision to remove
	nested sequences.

	Discussion on semantics group effort to simplify clocking at
	top level of properties and restrict event control on LHS of
	implication.

	Comments on clocking expression.  Erich commented that clocking is
	different than PSL with respect to a signal reference.  SystemVerilog
	only triggers on change of expression value, whereas PSL would evaluate.
	Action is to include statement in 17.4 that value will not the same
	as clocking value and sampling value.

17.11 - Multi-Clock:

	Need a figure:

	If clocks are same - same semantic as non-overlapping concatentation (##1)
	
	If clocks are different - then multi-clock concatentation
	
	Add note that intent is to have same implementation for single clock
	and multi-clock contanation.

	Question on precedence of event control relative to sequence operators.  There
	is no precedence defined, but it works as if it has lowest precedence of all
	sequence operators.  Concern is if grammer is amiguous.  Surrendra explained
	that if event control exists then it is a multi-clock sequence.  For clarity, 
	parantheses can be added.  BNF shoudl be extended to add the optional parentheses.

17.12 - Concurrent Assertions

	Adam questioned whether identifier can be placed in embedded context within always block.
	Action is to double check and ensure BNF allows for it as intent and requirement is to 	support naming of assertions.

17.12.2 - Embedding
	
	Comment on clock overriding property clock is wrong and stricken from document.

	The LRM indicates that multi-clocking of embedded assertions is not support.

17.13 - Clock Resolution

	Adam pointed out that BNF does not allow assertions within clocking domain.  This is 
	an issue that needs to be fixed.  Will also check program block.

17.14 - Grouping of Assertions

	Discussion on limits of templates. Adam indicated if used in procedural embedding it
	would be restricted to only cover or assert statements. Adam see's that it is quite
	limited.  Adam suggest adding module or generate_item to capability.  Faisal agreed
	to include in LRM.

17.15 - Bind

	Issue from last meeting discussing restrictions on program block.  Suggestion is
	to extend BNF to allow module instantiation or instance instantiation.

	Module/Program/Interface would be as if included within the block

3. Other Issues

	Adam - restrictions on where assertions can occur

	Adam - immediate assertions action block.  Can immediates occur within action block ?  		Yes they can. But cannot put concurrent asserions in any action block.
	
4. Next Steps

	Updated LRM will be out on Friday afternoon, need review by Monday AM for hand-off to 		Stu.

	Draft 5 will be out by Tuesday and will be reviewed in next Thursday's SV-AC
	
Meeting Concluded